[spi_device] V1 Signoff

[msfschaffner]

Description

Ensure V1 signoff criteria are fulfilled after focus area changes have landed.

[a-will]

Note that this will need updates to the test plan, since generic mode has been deleted.

[hcallahan-lowrisc]

Some M2 DD items (e.g. removal of Generic Mode, Removing the filter CSR, Potential Logic Optimizations) should not have a significant impact in terms of expected DV effort, so I'm going to reduce this effort slightly. @johngt

[antmarzam]

Commits since Earlgrey-ES tapeout

git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/spi_device/ hw/dv/sv/spi_agent/

599ab38 [spi_device] Update block diagram for TPM / generic mode
2d1e029 [spi_device] Add read pipeline diagram
1d2e3fe [spi_device] Remove data transfer diagram
094cb9f [spi_device] TPM port name change: rst_n -> rst_ni
2f0b933 [spi_device] Fix up TPM synchronization between domains
4ed1a8f [spi_device] Add synchronous clear to spid_fifo2sram_adapter
9b5f4e0 [spi_device] Clean up TPM address check
cbda9ea [spi_device] Fix up TPM command handling
0d14dd6 [docs] Fix repetitions of the definite article
39cfb3e [spi_device] Remove all timing mode CSRs
4c3debe [spi_device] Document the high-speed read pipeline
7f855dc [spi_device] Add pipelined reads for flash / passthrough
f28b713 [spi_device] Remove generic mode mentions
56c127c [spi_device] Write mode and status bits alongside command
d914f75 [spi_device] Enable continuously polled status registers
aff3fbd [reggen] Add unused we field statement for hwext
81cfbe0 [spi_device] Harmonize address mode syncs to byte beats
40a6ace [spi_device] Relax stringent CSB pulse width requirements
61a237e [util/reggen] reverse order of substruct generation
f83506b [spi_device] Add params for DPRAM offsets
f554d45 [spi_device] Add support for 1r1w RAMs and parity init
fc84846 [reggen,hw] Create index parameter for registers windows
726cd46 [spi_device] Remove generic mode
de31bdf [reggen] Remove the devmode input
963a500 [doc] Minor tweak to md sanitisation code
f91b5b4 [spi_device] Add 'features' list to spi_device.hjson
1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
59f8142 [doc] Moved badges over to using hosted images
e85f47c [doc] spi_device registers and interfaces now use CMDGEN
7688e71 [reggen] Add initial support for version and cip_id hjson fields
fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
0ba10b3 [reggen] Add CIP_IDs and bump all major versions
9378305 [regtool] Correct register QE assignment

Issues closed since the Earlgrey-ES tapeout

DD (& DV)

• [spi_device] Optimize CS pin on at most 1-2 pinmux paths #21538
• [spi_device] Change of interrupt types to status #21207
• [spi_device] Synchronize control and status bits at regular intervals #20754
• [spi_device] TPM poorly handles aborted transactions #20654
• [spi_device] Unsafe output enable timing in spi_p2s #18687
• [spi_device] Incoming address size cannot be validated #16411
• [spi_device] SPI pass-through does not support mode 3 #16339
• [spi_device] TPM interrupt for Write FIFO #15785
• [spi_device] Dummy CSB may trigger an upload interrupt #15721
• [spi_device] SW fails to update addr_4b_en in the middle of sim #15543
• [spi_device] Remove Generic (a.k.a. FwMode) from SPI_DEVICE HWIP #15452 -> There's an open PR removing the generic mode from the testplan [dv] SPI Device testplan generic mode removal #21579
• [spi_device] TPM FIFOs in DPSRAM #14045
• [spi_device] Widen TPM WrFIFO to 32-bit #13996
• [spi_device] Chip Select glitch detector #12747
• [spi_device] Auto-generated macros for reserved areas in the buffer #11740
• [spi_device] SDC updates & Enhance pass-through rates for wider reads by pipelining the return path #11718
• [spi_device] Check if CSb deasserted in the middle of byte transfer in Generic Mode #10058

Not planned DD (& DV)

• [spi_device] TPM DATA_FIFO / command buffer sizing #21159
• [spi_device,rtl] Consider adding signalling mechanism to abort  #18357
• [spi_device] Add an enable bit for the IP to prevent partial configuration? #14665
• [spi_device] payload upload ignores dummy cycles  #14051
• [spi_device] Check whether clock inverter can be removed #13437
• [spi_device] Recoverable last_read_addr #10038
• [spi_device] abort_done implementation #9823
• [ip/spi_device] confusing names on register status.txf_empty/full, rxf_empty/full #1212

DV

• [spi_device/dv] Verify CDC path when switching to/out of FW mode #15457

Doc

• [spi_device] Document update needed for flash/passthrough mode #15463
• [doc] Possible error(s) in SPI Device HWIP Technical Specification - Block Diagram #1827

Currently open issues

The following issues do not need resolving yet as we're doing V1 sign-off at this point.

DD (& DV)

• [spi_device] Disallow certain state changes when busy #21700
• [spi_device] TPM return-by-hw flawed without hardware write support #21160
• [spi_device,rtl] Handle SRAM integrity error output decisively #18353
• [spi_device,rtl] Potential logic optimizations in RTL #18354
• [spi_device] Late CSb de-assertion for op-complete commands #15517
• [spi_device] Remove filter CSR #14831
• [spi_device] Tagging for Upload Command/Address FIFOs and Payload Buffer #12439
• [spi_device] fifo2sram_adapter enhancement #12054
• [spi_device] Add an event for unexpected host behavior #10037
• [spi_device] Read Status, Read JEDEC ID, Read SFDP to have fixed value (read-only) in CMD_INFO #10009

DV

• [spi_device/dv] Update scoreboard to track dynamically-updated status registers #21111
• [spi_device] Scoreboard loses track of pending Read Buffer interrupts triggered at transaction end #20964 -> PR opened for this (Spi device readbuf interrupt tb fix #21712)
• [spi_device] Improvements/fixes to SPI device constants #20193
• [spi_device,dv] Track outstanding effort to bring covergroups above 90% #19081
• [spi_device,dv] stress_all test is flaky #19080
• [spi_device,dv] Add assertion to test SRAM logic is faster than update of current_address_i. #18352

Coverage report from 25/02/2024

The following report comes from the nightly regression dashboard (hash#49a27e136c)

The passing rate for the nightly regression above meets V1 sign-off criteria.
Currently all the V1 tests are passing at 100% pass rate.
For the overall (including V2, V2s and V3) the passing rate is over 94% for all tests with the vast majority being at 100% pass rate.

Summary

There has been a major refactor of spi device including the removal of the generic mode as well as changes which affect both TPM and flashmodes.

[antmarzam]

@rswarbrick / @hcallahan-lowrisc Can you review and let me know if the sign-off looks good?
Spi-device DV sign-off is definitely over V1 standards. Is it possible to sign it off at V2/V2S instead?
The screenshot above showing 52.78% progress for V2 is a bit misleading since quite a few of V2 tests on that list are part of the generic mode which is being removed from the testplan in #21579

[rswarbrick]

We've just had a V1 review meeting (@a-will, @antmarzam, @hcallahan-lowrisc, @rswarbrick). Notes here.

We're happy that all V1 checklist items are addressed, although we spotted a couple of minor action items that we'll try to handle immediately.

• [spi_device,dv] Update testbench to mention new flash_status bits, mode and read pipeline #21862
• [spi_device,dv] Drop explicit mentions of 2-port RAMs in testplan #21863
• [spi_device,dv,doc] Remove mentions of generic mode and 2-port SRAMs from dv document #21864

These action items don't themselves gate V1 signoff, so we're happy to mark the block as V1 at this point.

[a-will]

We're technically supposed to leave this open until the specific commit that changes the state is merged, but... I rolled back spi_device to V1, not V0, so there won't be such a commit. 😂

[rswarbrick]

Oops! I'll claim that I'd carefully thought about this... :-)