[spi_device] Chip Select glitch detector

[eunchan]

Many SPI_DEVICE logics rely on a clean Chip Select signal. If Chip Select signal has glitches, the SPI_DEVICE behaves incorrectly. This issue is to add CS glitch detectors (two: one for SPI, other for TPM).

The glitch detectors catch CS assertion and deassertion without enough SPI CLK edges:

• register is reset to 1 by CSb
• register is cleared to 0 by csb_assertion_pulse
• register is latched by clk_csb (not sure this is plausible as register's reset is CSb also)
• the latched value is compared to 1 at sys_csb_deasserted_pulse. If the value is 1, then report error to the SW.

It may not be possible to use CSb as a reset, in that case the register may be reset by sys_rst_ni & ~sys_csb_deasserted_pulse.

CC: @tjaychen

Effort estimate by @hcallahan-lowrisc:

Note that there is a number of open issues about CSB behaviour and robustness to errors, so some estimated effort (if deemed necessary) may overlap between those issues. (#10058 #12747 #15517 #15721)

estimate 12
remaining 2023-03-23 12

[andreaskurth]

Triaged for spi_device. Assigning to M2.5 with Priority:P2 Priority: medium because even though this is about robustness in an environment with errors, we should check with the product team if the behavior of spi_device is acceptable. If yes, we can defer this to Type:FutureRelease Not relevant to currently planned releases/milestones .

[hcallahan-lowrisc]

Note that there is a number of open issues about CSB behaviour and robustness to errors, so some estimated effort (if deemed necessary) may overlap between those issues. (#10058 #12747 #15517 #15721)

estimate 12
remaining 2023-03-23 12

[moidx]

@moidx to check if there are glitch suppression requirements that can be added to the IO pads (for integration purposes).

[zi-v]

The IO slice has a configurable Schmitt trigger which suppresses pulses on transition if enabled. If this configuration input to the IO slice can be controlled/set by SW, the chance of catching a glitch on SPI in a well designed system is negligible.

[a-will]

This issue is confusing, and I'm not sure what it's about. For SPI, PCB-level SI is up to the I/O buffers and the PCB design, and I think we should keep it that way.

However, logic that relies on sampling CSB to effect CDC of events may need a closer look. For flash and TPM modes, there should be no new events before at least 8 SCK cycles (smallest command), and any running state leading up to an event trigger should be thrown out on CSB release.