[spi_device] Optimize CS pin on at most 1-2 pinmux paths

[moidx]

Description

The current timing constraints for SPI TPM CS try to optimize timing against all muxable IO configurations. This causes timing convergence issues, and we won't be able to support this in the silicon PROD iteration.

Silicon integrations should be constrained to using 1 or 2 pin mapping locations for the TPM CS signal.

@brendose is it ok to define a constraint for this on the integration pinouts? If so, can you provide feedback on which pins to use? It would be ideal if this also falls in the outer ring of the package in case we have to support a single package for multiple use cases.

CC: @msfschaffner, @a-will

[moidx]

We'll also have to update the top-level documentation to capture this.

[moidx]

Let's allocate IOA2 for TPM CS.

@brendose is confirming this with @jesultra.

[jettr]

We are currently using IOA7 for SPI_CSB, can we use that instead of IOA2

[moidx]

We are currently using IOA7 for SPI_CSB, can we use that instead of IOA2

Yes, we can use IOA7 instead. If there are no objections we can close this issue once the SDC file constraints are updated to use this pin.

Thanks everyone!

[brendose]

No objections from hardware side. IOA7 is suitable.

[jesultra]

As Jett said, IOA7 is the pin that ChromeOS planned to use for SPI TPM CS, and if the hardware can support only one pin, that should be it. If the hardware could support limited mux'ing between two pins, then we would want to be able to select either IOA7 or IOA2. The latter would help in a hypothetical future scenario, in which the OT chip would simultaneously support I2C (on IOA7/8) and SPI TPM.