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This is a DV companion issue to #20754. When the SPI domain begins updating status registers at every byte beat (8th posedge of SPI clock), the Read Status command will no longer return a static value. Consequently, validation of Read Status commands will need to be updated to support tracking changes that occur at every byte beat.
The design PR will initially disable this section of the code:
In addition, the core clock (sys_clk) domain will continue to update its view only at CSB de-assertion time. As a result, the scoreboard's current strategy of using csr_rd() to determine the resolved value (of software and hardware updates at commit time) will no longer work. latch_flash_status() currently represents what happens to both the SPI domain source-of-truth and the sys_clk domain's view, but the update rate for these two domains is no longer the same.
Note that the passthrough gate's "view" of the BUSY bit also continues to only update at CSB de-assertion time.
Here's a list of timings to keep in mind:
(byte beat) SPI domain commits a newly-resolved flash status register value.
(byte beat) The latest committed value of the flash status register is prepared for the next response byte for any ongoing Read Status command.
(CSB posedge) The current value of the BUSY bit becomes the committed value for the passthrough gate enable.
(CSB posedge) Delayed by a synchronizer, the core clock domain picks up the current value of the flash status register.
The text was updated successfully, but these errors were encountered:
Description
This is a DV companion issue to #20754. When the SPI domain begins updating status registers at every byte beat (8th posedge of SPI clock), the Read Status command will no longer return a static value. Consequently, validation of Read Status commands will need to be updated to support tracking changes that occur at every byte beat.
The design PR will initially disable this section of the code:
opentitan/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
Lines 587 to 593 in efc45b7
In addition, the core clock (sys_clk) domain will continue to update its view only at CSB de-assertion time. As a result, the scoreboard's current strategy of using
csr_rd()
to determine the resolved value (of software and hardware updates at commit time) will no longer work.latch_flash_status()
currently represents what happens to both the SPI domain source-of-truth and the sys_clk domain's view, but the update rate for these two domains is no longer the same.Note that the passthrough gate's "view" of the BUSY bit also continues to only update at CSB de-assertion time.
Here's a list of timings to keep in mind:
The text was updated successfully, but these errors were encountered: