sim_riscv_zmmul

sim/riscv: Fix RISC-V multiply instructions on simulator

• Status: Merged for GDB 13
• Branch: sim-riscv-zmmul
• Tracking PR: #41 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-08-31)
  • PATCH v1 (PING 1) (2022-09-14)
  • PATCH v1 (PING 2) (2022-09-21)
  • PATCH v1 (PING 3) (2022-10-06)

Based On

• Extension: Zmmul

Issue Solved

After adding the Zmmul extension, the simulator is broken.

The cause is simple. The RISC-V simulator supports I, M and A extensions and the instruction is identified by those instruction classes:

• INSN_CLASS_I (for I)
• INSN_CLASS_M (for M)
• INSN_CLASS_A (for A)

After adding the Zmmul extension, INSN_CLASS_M is splitted to:

• INSN_CLASS_ZMMUL (multiply instructions)
• INSN_CLASS_M (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My patchset fixed that and I added a testcase (checks whether all RV32M instructions run without any fault) but only opcodes part is applied so it's now broken state for the simulator.

My patchset is merged with almost completely written commit message by Andrew Burgess.