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riscv_dis_arch_priv_spec
Tsukasa OI edited this page Nov 20, 2022
·
7 revisions
- Branch:
riscv-dis-arch-priv-spec
- Tracking PR: #29 (view Pull Request and Diff)
- Mailing List:
- PATCH v3 (2022-11-20) - binutils | gdb-patches
-
Disassembler: Add
arch
disassembler option
Version count is derived from this. - Disassembler: Make ELF
priv-spec
overridable
(TODO)
This is not hypothetical and even has a problem on ELF files.
OpenSBI is the prime example.
OpenSBI can be compiled with the current RISC-V GNU Toolchain (with privileged specification version 1.11) but uses hypervisor instructions.
It also has ELF arch attribute "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
(RV64GC
with ISA version 2.2) if we compile for RV64 so there's no H
-extension reference here.
An Excerpt from the Source Code (OpenSBI 1.1, lib/sbi/sbi_hfence.S
):
.align 3
.global __sbi_hfence_gvma_vmid_gpa
__sbi_hfence_gvma_vmid_gpa:
/*
* rs1 = a0 (GPA >> 2)
* rs2 = a1 (VMID)
* HFENCE.GVMA a0, a1
* 0110001 01011 01010 000 00000 1110011
*/
.word 0x62b50073
ret
- Target:
fw_jump.elf
from OpenSBI 1.1 (RV64) - Compiler/Toolchain: RISC-V GNU Toolchain 2022.06.10
- Command:
riscv64-unknown-elf-objdump -d fw_jump.elf
00000000800097c8 <__sbi_hfence_gvma_vmid_gpa>:
800097c8: 62b50073 .4byte 0x62b50073
800097cc: 8082 ret
800097ce: 0001 nop
- Command:
riscv64-unknown-elf-objdump -M arch=rv64gch -d fw_jump.elf
00000000800097c8 <__sbi_hfence_gvma_vmid_gpa>:
800097c8: 62b50073 hfence.gvma a0,a1
800097cc: 8082 ret
800097ce: 0001 nop
Even after this patchset, only 1 of 8 hfence.*
instructions is correctly disassembled but the reason is separate: OpenSBI uses .word
, not .insn
(the disassembler handles some instructions emitted with .word
as data). In this case, objdump -D
may be a workaround.