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riscv_bfloat16
- Branch:
riscv-bfloat16 - Tracking PR: #115 (view Pull Request and Diff)
- Mailing List:
- REVIEW ONLY (2023-08-03)
This patch set implements three extensions in the RISC-V BF16 Extensions specification: https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999
Each patch implements following extensions one by one (PATCH 1-3/4).
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Zfbfmin(scalar BF16 conversion extension) -
Zvfbfmin(vector BF16 narrowing/widening conversion-only extension) -
Zvfbfwma(vector BF16 widening multiply-accumlate extension)
The extension versions are set to "0.8" as in the documentation (not final "1.0").
Although it's small, it covers some of important machine learning workloads (especially Zvfbfwma extension). I hope this branch helps testing this draft extension on the simulator.
PATCH 4/4 is a tentative support of an assembler directive: .bfloat16.
Although not included in the RISC-V Assembly Programmer's Manual, the final assembler directive will be likely .bfloat16 (like x86 and AArch64). Test cases are ported from AArch64.