riscv_long_insn_1

RISC-V: Better support for long instructions (64 < x <= 176 [bits])

• Status: Merged for Binutils 2.40
• Branch: riscv-long-insn-1
• Tracking PR: #91 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-11-19)
  • PATCH v2 (2022-11-23)
  • PATCH v3 (2022-11-25)
  • PATCH v4 (2022-11-25)

Issue Solved

Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") was suddenly merged into master by Jan Beulich. Although this encoding is not considered frozen (see the section "Expanded Instruction-Length Encoding" in the ISA Manual), such attempt makes sense.

However, it was insufficient in some ways. I quickly found a stack-based buffer overflow and fixed that. Besides that, I found following issues related to long (assembler: .insn-based, disassembler: unrecognized and printed as .byte) instructions:

1. Assembler: False "value conflicts with instruction length" error
2. Assembler: DWARF line number information is missing with big numbers
3. Disassembler: Instruction is trimmed with 64-bits

Related

• Fix: stack-based buffer overflow caused by riscv_insn_length change