Patches Processed

For ongoing work, see Patch Queue.

For withdrawn / combined works, see Patch Withdrawn.

For Binutils 2.39

Merged

• QUICK fix on Li's Zhinx implementation (all functional part)
• Combined floating point enhancements (only partially)
• Extension: Privileged Arch 1.12 and More CSRs (only Privileged Architecture 1.12 CSRs are merged)
• Extension: Smstateen, Sscofpmf and Sstc CSRs (with additional CSR feature gate handling)
• Extension: Zicbom, Zicbop and Zicboz
• Extension: version of Zihintpause
• Extension Handling: Fix canonical extension order (K and J)
• Extension Handling: Canonical ordering of H
• Fix: Fix mask for some fcvt instructions
• Fix: Make ISA parser stricter (with code clarity improvement) (strict parser was based on my misunderstandings but small optimization is merged)
• Fix: Remove RV128-only fmv instructions
• Fix: RV32Q conflict no longer exists
• I18N: Consistency Fix (June 2022) (RISC-V portion)
• I18N: Enablement on error messages (required extension names)

Rejected

• Fix: Make ISA parser stricter (with code clarity improvement) (main portion is rejected because it was based on my misunderstandings)

For Binutils 2.40

Merged

• Disassembler: Fix address printer (non-tidying part merged)
• Disassembler: Fix types and styles
• Disassembler: Tidying for Optimization (Batch 1)
• Extension: Zmmul
• Extension: Multiple extensions from RISC-V Profiles (Ssstateen portion)
• Fix: Set ELF flag of Ztso on .option arch
• Fix: riscv_set_tso declaration
• Fix: stack-based buffer overflow caused by riscv_insn_length change (Binutils part)
• Fix: Build failure on RISC-V mapping symbol handling with GCC 12
• Fix: RV32EF conflict no longer exists
• Linker: Allow merging H extension
• RISC-V: Fix CSR accessibility on vector (without some tests)
• RISC-V: Add privileged extensions without instructions/CSRs
• RISC-V: Workaround for CSR implications to the Privileged Architecture
• RISC-V: Zfinx-related fixes (1)
• RISC-V: Better support for long instructions (64 < x <= 176 [bits])
• psABI: Add testcase for DWARF register numbers
• psABI: Assign DWARF register numbers to vector registers
• GAS: Add OP_V to .insn directive
• GAS: Improve "bits undefined" diagnostics
• GAS: Fix a broken testcase (2022-08-05)
• I18N: Consistency Fix (June 2022) (Mach-O portion)
• Cleaning: Move RISC-V supervisor instructions after all unprivileged ones
• Cleaning: Opcode Tidying - Operands (Batch 1)
• Cleaning: Opcode Tidying (Hints)
• Cleaning: Move certain Arrays
• Cleaning: Logic for State Enable extensions (merged: 1 of 2)
• Clang: Stop using -Wstack-usage=262144 when built with Clang
• Clang: Remove/mark unused variables (bfd, binutils and gas)
• Clang: Suppress warnings if built with Clang (gold)
• Clang: Suppress warnings if built with Clang (gdb)
• configure: Pass CPPFLAGS_FOR_BUILD to subdirectories
• Cleaning: Remove unused substitution (binutils, @PROGRAM@)
• gdb, opcodes: Add non-enum disassembler options (pushed as a new committer)

Rejected

• Fix: Declare getopt function on older GNU libc
  (short-term fix is submitted as sim: Use getopt_long instead of getopt)

For GDB 13

Merged

• Fix: stack-based buffer overflow caused by riscv_insn_length change (GDB part)
• sim: Update mailing list address
• sim: Use getopt_long instead of getopt
• sim/riscv: Complete tidying up with SBREAK
• sim/riscv: Fix RISC-V multiply instructions on simulator
• sim/moxie: Add custom directory stamp rule
• gdb, opcodes: Add non-enum disassembler options (GDB part pushed as a committer)
• gdbsupport: Fix config.status dependency
• Clang: Suppress some general warnings if built with Clang (gdb)
• Clang: Suppress warnings if built with Clang (sim)
• Clang: Suppress warnings if built with Clang (sim: printf-like functions)
• Clang: Suppress warnings if built with Clang (sim and gdb, big batch 1) (5 patches upstreamed)
• GCC: Define macro to disable -Wdeprecated-declarations
• gdb/xcoffread: Remove unused extra_lines variable
• Cleaning: Remove unused substitution (sim, @CXXFLAGS@)

Rejected

• Disassembler: Optimization: Cache per-BFD disassembler
  (Preparing second proposal)

For Binutils 2.41

Merged

• Extension: Zvkt (Vector Data-Independent Execution Latency; after release branching)
• Cleaning and Optimization: Linker Relaxation Passes
• Cleaning: Allocate "Various" Operand Type
  (as a part of others' upstream Zfa work)

For GDB 14

Merged

• gdb: Regenerate certain files using the maintainer mode (January 2023) (sim part)
• sim: Move getopt checking inside SIM_AC_PLATFORM
• Fix: Stub VLEN support on GDB (1)

For Binutils 2.42

Merged

• ISA: ratified RV32E and RV64E (Binutils Part)
• Extension: Zihintntl (Non Temporal Locality Hint)
• Extension: Code size reduction version 1.0.4-1
• Extension: Version of Ztso
• Extension: Remove non-existing Zve32d
• Extension: Implication from Zve32x to Zicsr
• Extension: Zvfh and Zvfhmin (Vector FP16 Operations)
• Extension: Zvkt (Vector Data-Independent Execution Latency)
• Extension: Smcntrpmf (Cycle and Instret Privilege Mode Filtering)
• Extension: Svadu (Hardware Updating of PTE A/D Bits)
• Extension: Make XVentanaCondOps instructions RV64-only
• Fix: Add conflicting combination E and H
• Fix: Opcode entries of vmsge{,u}.vx
• Fix: Make T-Head testing pattern more generic
• Fix: Make fli.h also available to Zfa + Zvfh
• Cleaning: Remove semicolons from DECLARE_INSN entries
• GAS: Enable RVC when Zca is enabled via .option arch
• ...and 4 commits to fix typos