riscv_dis_opts_cache_support

Disassembler: Cache instruction class support

• Status: Waiting for a prerequisite to be Merged
• Branch: riscv-dis-opts-cache-support
• Tracking PR: #22 (view Pull Request and Diff)
• Mailing List:
  • Not yet

Requires

• Disassembler: Minor optimizations (batch 1)
  • Requires: Disassembler: Use faster hash table

Project: Disassembler Performance Improvements

Aggregate performance benchmark should be available here.

1. Disassembler: Use faster hash table
2. Disassembler: Minor optimizations (batch 1)
3. (You are here) Disassembler: Cache instruction class support

Feature Description

As I mentioned in the previous patchset, calling riscv_subset_supports repeatedly harms the performance in a measurable way (about 3-13% in total).

As a simple solution, this patch now caches instruction class support as a signed char array.

Performance Improvements

On disassembling linked RISC-V ELF files using objdump, performance improvements achieved by this patchset is about 5-8%. Not bad for a simple change.

This is relative to the previous optimization.

objdump (ELF)

Program	Improvements	Notes
Busybox 1.35.1 (RV64GC)	6.0-6.9%
OpenSBI 1.1 (generic fw_*.elf)	4.6-8.0%
Linux kernel 5.18 (vmlinux)	5.3-6.1%
Linux kernel 5.18 (vmlinux.o)	(-0.5)-2.2%	Not finally linked
glibc (libc.so.6)	5.6-6.9%

objdump (ELF-based archive)

Program	Improvements
glibc (libc.a)	0.1-0.6%
newlib (libc.a)	0.7-2.0%

objdump (binary)

Program	Improvements
Linux kernel 5.18 (vmlinux)	7.9-9.4%
Random files (/dev/urandom)	8.2-9.3%
1M (1048576) CSR instructions	40.4%

gdb: disas of near all code region

Program	Improvements
Linux kernel 5.18 (vmlinux) with debug info	1.0%
Linux kernel 5.18 (vmlinux) without debug info	1.3%
OpenSBI 1.1 (generic fw_*.elf)	1.1-3.5%
1M (1048576) CSR instructions (ELF)	7.8%