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en devel environment
This page describes the development environment required for RSD.
The environment depends on what you want to do.
This page considers the following three purposes.
- Software simulation
- Boot on Xilinx Zynq FPGA boards
- Synthesis for ASIC (experimental)
Please read this page carefully and setup required OS, tools, and packages.
The version of each software that we tested is also listed, but RSD could work with other versions.
Cygwin on Windows or Linux can be used, depending on your purpose.
OS | Tested version | |
---|---|---|
Software simulation | Windows Linux |
Cygwin on Windows 10 Debian 8 Ubuntu 18.04 |
Boot on Xilinx Zynq FPGA boards | Linux | Debian 8 Ubuntu 18.04 |
Synthesis for ASIC | Linux | Debian 8 Ubuntu 18.04 |
The followings are required for all the three purposes on both Windows and Linux.
Tested version | |
---|---|
Git | |
Python 3 | 3.4.2 |
GCC (x86-64) | 6.5.0 |
GCC (RISC-V) | 8.1.0 |
One of the following is also required to simulate RSD on software simulators.
Tested version | |
---|---|
Mentor QuestaSim | 2019.4.2 |
Mentor ModelSim | |
Verilator | 4.026 3.922 |
Xilinx Vitis | 2019.2.1 |
The followings are also required to boot RSD on Xilinx Zynq FPGA boards.
Tested version | |
---|---|
Synopsys Synplify | M-2017.03-SP1 |
Xilinx Vitis (including Vivado) | 2019.2.1 |
In addition, run the following commands to install necessary packages via apt-get.
sudo ln -s /usr/bin/make /usr/bin/gmake # If you use Ubuntu
sudo apt-get install u-boot-tools ntp device-tree-compiler
The following is also required to synthesize RSD for ASIC.
Tested version | |
---|---|
Synopsys Design Compiler | O-2018.06-SP4 |
- Pipeline viewer Konata
- Download and extract the pre-built binary archive.
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Visual Studio Code
- Please install SystemVerilog extension after introduction.
- We strongly recommend to use svls-vscode.
You must also setup some environment variables after setting up the development environment.
Please see this wiki page for the details.