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xtensa: fix inline assembly of rsil in exception code for XCC #56790

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merged 1 commit into from
Apr 20, 2023

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XCC doesn't like the syntax using STRINGIFY. So parameterize the second argument to rsil.

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marc-hb commented Apr 12, 2023

Compilation still fails with the same error message as shared in

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Can you try the latest one? I removed the last colon of the line.

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marc-hb commented Apr 13, 2023

5175531 fixes the compilation issue with RG-2017.8-linux/XtensaTools !

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marc-hb commented Apr 13, 2023

Can you please add a Fixes commit ... ?

Commit 4084726 added inline
assembly to lock interrupt. However, XCC doesn't like the syntax
using STRINGIFY, and also an empty clobber section. So parameterize
the second argument to rsil, and remove the last colon.

Signed-off-by: Daniel Leung <[email protected]>
@dcpleung dcpleung marked this pull request as ready for review April 13, 2023 17:21
@zephyrbot zephyrbot added the area: Xtensa Xtensa Architecture label Apr 13, 2023
@marc-hb marc-hb added bug The issue is a bug, or the PR is fixing a bug priority: high High impact/importance bug labels Apr 14, 2023
@marc-hb marc-hb added the platform: Intel ADSP Intel Audio platforms label Apr 14, 2023
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Tested to work with the XCC RG-2017.8 toolchain we use for Intel cAVS2.5 platforms.

@nashif nashif merged commit 5def4ab into zephyrproject-rtos:main Apr 20, 2023
@dcpleung dcpleung deleted the xtensa/exc_xcc branch April 20, 2023 16:41
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area: Xtensa Xtensa Architecture bug The issue is a bug, or the PR is fixing a bug platform: Intel ADSP Intel Audio platforms priority: high High impact/importance bug
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