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xtensa: fix inline assembly of rsil in exception code for XCC #56790

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Apr 20, 2023
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xtensa: fix inline assembly of rsil in exception code for XCC #56790

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4 changes: 2 additions & 2 deletions arch/xtensa/core/xtensa-asm2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -302,8 +302,8 @@ void *xtensa_excint1_c(int *interrupted_stack)
* resulting it being zero before switching to another
* thread.
*/
__asm__ volatile("rsil %0, " STRINGIFY(XCHAL_NMILEVEL)
: "=r" (ignore) : : );
__asm__ volatile("rsil %0, %1"
: "=r" (ignore) : "i"(XCHAL_NMILEVEL));

_current_cpu->nested = 1;
}
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