xtensa: fix inline assembly of rsil in exception code for XCC

Commit 4084726 added inline assembly to lock interrupt. However, XCC doesn't like the syntax using STRINGIFY, and also an empty clobber section. So parameterize the second argument to rsil, and remove the last colon. Signed-off-by: Daniel Leung <[email protected]>
zephyrproject-rtos · Apr 13, 2023 · 7faed58 · 7faed58
1 parent 06d4a8b
commit 7faed58
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/arch/xtensa/core/xtensa-asm2.c b/arch/xtensa/core/xtensa-asm2.c
@@ -302,8 +302,8 @@ void *xtensa_excint1_c(int *interrupted_stack)
 		 *    resulting it being zero before switching to another
 		 *    thread.
 		 */
-		__asm__ volatile("rsil %0, " STRINGIFY(XCHAL_NMILEVEL)
-				: "=r" (ignore) : : );
+		__asm__ volatile("rsil %0, %1"
+				: "=r" (ignore) : "i"(XCHAL_NMILEVEL));
 
 		_current_cpu->nested = 1;
 	}