Fixes for DDR initialization. Improvements to DCFG, MP and Timers.

config/examples/nxp-t2080.config

@@ -30,6 +30,7 @@ ARCH_FLASH_OFFSET?=0xEFFF0000
 BOOTLOADER_PARTITION_SIZE=0x10000
 
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFFD0000
+WOLFBOOT_LOAD_ADDRESS?=0x19000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFFB0000
 
 # Location of temporary sector used during updates

hal/nxp_p1021.c

@@ -902,7 +902,7 @@ static int hal_flash_init(void)
     return ret;
 }
 
-void hal_ddr_init(void)
+static void hal_ddr_init(void)
 {
 #ifdef ENABLE_DDR
     uint32_t reg;
@@ -967,6 +967,12 @@ void hal_ddr_init(void)
 #endif /* ENABLE_DDR */
 }
 
+void hal_early_init(void)
+{
+    hal_ddr_init();
+}
+
+
 #ifdef ENABLE_PCIE
 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
 #define CONFIG_SYS_PCIE1_IO_PHYS  0xffc20000

hal/nxp_ppc.h

@@ -69,7 +69,7 @@
 
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
-    #if 1
+    #if 1 /* DDR must be enabled before CPC L2SRAM */
         #define L1_CACHE_ADDR (0xF8F80000) /* L1 as SRAM */
     #else
         #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
@@ -282,6 +282,8 @@
 
     #define CPCHDBCR0_SPEC_DIS  (0x80000000 >> 4)
 
+    #define CORENET_DCSR_SZ_1G  0x3
+
     /* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
     #define LAWBAR_BASE(n) (0xC00 + (n * 0x10))
     #define LAWBARH(n)     *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0))

hal/nxp_t1024.c

@@ -71,25 +71,23 @@ static int test_tpm(void);
 #define LCC_BSTAR_LAWTRGT(n) ((n) << 20)
 #define LCC_BSTAR_LAWSZ(n)   ((n) & 0x3F)
 
-#define ECM_BASE             (CCSRBAR + 0x1000)
-#define ECM_EEBACR           ((volatile uint32_t*)(ECM_BASE + 0x00)) /* ECM CCB address configuration register */
-#define ECM_EEBPCR           ((volatile uint32_t*)(ECM_BASE + 0x10)) /* ECM CCB port configuration register */
-#define ECM_EEBPCR_CPU_EN(n) ((n) << 24)
-
-/* Global Utilities (GUTS) - DCFG (Device Configuration/Pin Control) T1024RM 7.3 */
-#define GUTS_BASE      (CCSRBAR + 0xE0000)
-#define GUTS_PVR       ((volatile uint32_t*)(GUTS_BASE + 0xA0UL))
-#define GUTS_SVR       ((volatile uint32_t*)(GUTS_BASE + 0xA4UL))
-#define GUTS_DEVDISR1  ((volatile uint32_t*)(GUTS_BASE + 0x70UL)) /* Device disable register */
-#define GUTS_DEVDISR2  ((volatile uint32_t*)(GUTS_BASE + 0x74UL)) /* Device disable register */
-#define GUTS_DEVDISR3  ((volatile uint32_t*)(GUTS_BASE + 0x78UL)) /* Device disable register */
-#define GUTS_DEVDISR4  ((volatile uint32_t*)(GUTS_BASE + 0x7CUL)) /* Device disable register */
-#define GUTS_DEVDISR5  ((volatile uint32_t*)(GUTS_BASE + 0x80UL)) /* Device disable register */
-#define GUTS_COREDISR  ((volatile uint32_t*)(GUTS_BASE + 0x94UL)) /* Core Enable/Disable */
-
-#define RCPM_PCTBENR    ((volatile uint32_t*)(CCSRBAR + 0xE21A0)) /* Physical Core Time Base Enable Bit 0=Core 0 */
-#define RCPM_PCTBCKSELR ((volatile uint32_t*)(CCSRBAR + 0xE21A4)) /* Physical Core Time Base Clock Select 0=Platform Clock/16, 1=RTC */
-#define RCPM_TBCLKDIVR  ((volatile uint32_t*)(CCSRBAR + 0xE21A8)) /* Time Base Clock Divider 0=1/16, 1=1/8, 2=1/24, 3=1/32 */
+/* DCFG (Device Configuration/Pin Control) T1024RM 7.3 */
+#define DCFG_BASE      (CCSRBAR + 0xE0000)
+#define DCFG_PVR       ((volatile uint32_t*)(DCFG_BASE + 0xA0UL))
+#define DCFG_SVR       ((volatile uint32_t*)(DCFG_BASE + 0xA4UL))
+#define DCFG_DEVDISR1  ((volatile uint32_t*)(DCFG_BASE + 0x70UL)) /* Device disable register */
+#define DCFG_DEVDISR2  ((volatile uint32_t*)(DCFG_BASE + 0x74UL)) /* Device disable register */
+#define DCFG_DEVDISR3  ((volatile uint32_t*)(DCFG_BASE + 0x78UL)) /* Device disable register */
+#define DCFG_DEVDISR4  ((volatile uint32_t*)(DCFG_BASE + 0x7CUL)) /* Device disable register */
+#define DCFG_DEVDISR5  ((volatile uint32_t*)(DCFG_BASE + 0x80UL)) /* Device disable register */
+#define DCFG_COREDISR  ((volatile uint32_t*)(DCFG_BASE + 0x94UL)) /* Core Enable/Disable */
+#define DCFG_BRR       ((volatile uint32_t*)(DCFG_BASE + 0xE4UL))  /* Boot Release Register (DCFG_CCSR_BRR) */
+#define DCFG_DCSR      ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */
+
+#define RCPM_BASE       (CCSRBAR + 0xE2000)
+#define RCPM_PCTBENR    ((volatile uint32_t*)(RCPM_BASE + 0x1A0)) /* Physical Core Time Base Enable Bit 0=Core 0 */
+#define RCPM_PCTBCKSELR ((volatile uint32_t*)(RCPM_BASE + 0x1A4)) /* Physical Core Time Base Clock Select 0=Platform Clock/16, 1=RTC */
+#define RCPM_TBCLKDIVR  ((volatile uint32_t*)(RCPM_BASE + 0x1A8)) /* Time Base Clock Divider 0=1/16, 1=1/8, 2=1/24, 3=1/32 */
 
 /* MPIC - T1024RM 24.3 */
 #define PIC_BASE    (CCSRBAR + 0x40000)
@@ -389,8 +387,8 @@ enum ifc_amask_sizes {
 #define DDR_DEBUG_29       ((volatile uint32_t*)(DDR_BASE + 0xF70))
 
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */
-#define DDR_SDRAM_CFG_32_BE    0x00080000
 #define DDR_SDRAM_CFG_ECC_EN   0x20000000
+#define DDR_SDRAM_CFG_32_BE    0x00080000
 #define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
 #define DDR_SDRAM_CFG_BI       0x00000001 /* Bypass initialization */
 
@@ -656,14 +654,11 @@ static void hal_flash_init(void)
 #endif
 }
 
-void hal_ddr_init(void)
+static void hal_ddr_init(void)
 {
 #ifdef ENABLE_DDR
     uint32_t reg;
 
-    /* enable timebase on core 0 */
-    set32(RCPM_PCTBENR, (1 << 0));
-
     /* If DDR is already enabled then just return */
     if (get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) {
         return;
@@ -731,15 +726,6 @@ void hal_ddr_init(void)
     set32(DDR_SDRAM_CFG, (DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN));
     asm volatile("sync;isync");
 
-    /* busy wait for ~500us */
-    udelay(500);
-    asm volatile("sync;isync");
-
-    /* Enable controller */
-    reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
-    set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN);
-    asm volatile("sync;isync");
-
     /* Errata A-008378: training in DDR4 mode */
     /* write to DEBUG_29[8:11] a value of 4'b1001 before controller is enabled */
     reg = get32(DDR_DEBUG_29);
@@ -761,10 +747,19 @@ void hal_ddr_init(void)
     reg |= 0x0070006F; /* DDR-1400/1500/1600 */
     set32(DDR_DEBUG_29, reg);
 
+    /* busy wait for ~500us */
+    udelay(500);
+    asm volatile("sync;isync");
+
+    /* Enable controller */
+    reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
+    set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN);
+    asm volatile("sync;isync");
+
     /* Wait for data initialization to complete */
     while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) {
         /* busy wait loop - throttle polling */
-        udelay(1);
+        udelay(10000);
     }
 
     /* Errata A-009663 - Write real precharge interval */
@@ -780,6 +775,33 @@ void hal_ddr_init(void)
 #endif
 }
 
+
+void hal_early_init(void)
+{
+    /* enable timebase on core 0 */
+    set32(RCPM_PCTBENR, (1 << 0));
+
+    /* invalidate the CPC before DDR gets enabled */
+    set32((volatile uint32_t*)(CPC_BASE + CPCCSR0),
+        (CPCCSR0_CPCFI | CPCCSR0_CPCLFC));
+    while (get32((volatile uint32_t*)(CPC_BASE + CPCCSR0)) &
+        (CPCCSR0_CPCFI | CPCCSR0_CPCLFC));
+
+    /* set DCSRCR space = 1G */
+    set32(DCFG_DCSR, (get32(DCFG_DCSR) | CORENET_DCSR_SZ_1G));
+    get32(DCFG_DCSR); /* read again */
+
+    /* disable devices */
+    set32(DCFG_DEVDISR1,
+        ((1 << 19) | /* Disable USB1 */
+         (1 << 18) | /* Disable USB2 */
+         (1 << 15) | /* SATA1 */
+         (1 << 2)    /* DIU (LCD) */
+    ));
+
+    hal_ddr_init();
+}
+
 static void hal_cpld_init(void)
 {
 #ifdef ENABLE_CPLD
@@ -1049,7 +1071,7 @@ extern uint32_t _bootpg_addr;
 /* Startup additional cores with spin table and synchronize the timebase */
 static void hal_mp_up(uint32_t bootpg)
 {
-    uint32_t up, cpu_up_mask, whoami, bpcr, devdisr;
+    uint32_t up, cpu_up_mask, whoami, bpcr;
     uint8_t *spin_table_addr;
     int timeout = 50, i;
 
@@ -1068,18 +1090,11 @@ static void hal_mp_up(uint32_t bootpg)
     set32(LCC_BSTAR, LCC_BSTAR_EN | LCC_BSTAR_LAWTRGT(LAW_TRGT_DDR_1) | LAW_SIZE_4KB);
 
     /* Disable time base on inactive core */
-    devdisr = get32(GUTS_DEVDISR);
-    if (whoami)
-        devdisr |= GUTS_DEVDISR_TB0;
-    else
-        devdisr |= GUTS_DEVDISR_TB1;
-    set32(GUTS_DEVDISR, devdisr);
-
-    /* Enable the CPU core(s) */
+    set32(RCPM_PCTBENR, (1 << !whoami));
+
+    /* Release the CPU core(s) */
     up = ((1 << CPU_NUMCORES) - 1);
-    bpcr = get32(ECM_EEBPCR);
-    bpcr |= ECM_EEBPCR_CPU_EN(up);
-    set32(ECM_EEBPCR, bpcr);
+    set32(DCFG_BRR, up);
     asm volatile("sync; isync; msync");
 
     /* wait for other core to start */
@@ -1105,19 +1120,14 @@ static void hal_mp_up(uint32_t bootpg)
     }
 
     /* Disable our timebase */
-    if (whoami)
-        devdisr |= GUTS_DEVDISR_TB1;
-    else
-        devdisr |= GUTS_DEVDISR_TB0;
-    set32(GUTS_DEVDISR, devdisr);
+    set32(RCPM_PCTBENR, (1 << whoami));
 
     /* Reset our timebase */
     mtspr(SPRN_TBWU, 0);
     mtspr(SPRN_TBWL, 0);
 
     /* Enable timebase for all cores */
-    devdisr &= ~(GUTS_DEVDISR_TB0 | GUTS_DEVDISR_TB1);
-    set32(GUTS_DEVDISR, devdisr);
+    set32(RCPM_PCTBENR, (1 << 0) | (1 << 1));
 }
 
 static void hal_mp_init(void)

hal/nxp_t2080.c

@@ -381,7 +381,7 @@ static void hal_flash_init(void)
     IFC_CSOR(0) = 0x0000000C; /* TRHZ (80 clocks for read enable high) */
 }
 
-void hal_ddr_init(void)
+static void hal_ddr_init(void)
 {
 #ifdef ENABLE_DDR
     /* If DDR is already enabled then just return */
@@ -464,6 +464,11 @@ void hal_ddr_init(void)
 #endif
 }
 
+void hal_early_init(void)
+{
+    hal_ddr_init();
+}
+
 static void hal_cpld_init(void)
 {
 #ifdef ENABLE_CPLD

src/boot_ppc.c

@@ -33,7 +33,7 @@ extern unsigned int _start_data;
 extern unsigned int _end_data;
 
 extern void main(void);
-extern void hal_ddr_init(void);
+extern void hal_early_init(void);
 
 void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3,
     uint32_t mas7)
@@ -82,7 +82,7 @@ void invalidate_tlb(int tlb)
         mtspr(MMUCSR0, 0x2);
 }
 
-void __attribute((weak)) hal_ddr_init(void)
+void __attribute((weak)) hal_early_init(void)
 {
 
 }
@@ -91,7 +91,7 @@ void boot_entry_C(void)
 {
     register unsigned int *dst, *src, *end;
 
-    hal_ddr_init();
+    hal_early_init();
 
     /* Copy the .data section from flash to RAM */
     src = (unsigned int*)&_stored_data;