Fix for T1024 power on (must not use CPC L3 SRAM before DDR init).

wolfSSL · Sep 19, 2023 · 52cdd35 · 52cdd35
1 parent 603de31
commit 52cdd35
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Showing 5 changed files with 85 additions and 69 deletions.
diff --git a/config/examples/nxp-t2080.config b/config/examples/nxp-t2080.config
@@ -37,4 +37,5 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFFA0000
 
 # DTS (Device Tree)
 WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
diff --git a/docs/Targets.md b/docs/Targets.md
@@ -1242,8 +1242,8 @@ Board: T1024RDB
 Board rev: 0x3031
 CPLD ver: 0x42
 
-T1024E, Version: 1.0, (0x85480010)
-e5500, Version: 2.1, (0x80241021)
+T1024E, Version: 1.0, (0x8548_0010)
+e5500, Version: 2.1, (0x8024_1021)
 
 Reset Configuration Word (RCW):
 00000000: 0810000e 00000000 00000000 00000000

diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
@@ -41,8 +41,8 @@
         /* First stage loader features */
 
         #define ENABLE_L2_CACHE
-        #define L2SRAM_ADDR    (0xF8F80000) /* L2 as SRAM */
-        #define L2SRAM_SIZE    (256 * 1024)
+        #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
+        #define L2SRAM_SIZE   (256 * 1024)
     #else
         /* For wolfBoot features */
         #define ENABLE_L1_CACHE
@@ -55,7 +55,7 @@
     #endif
 
 #elif defined(PLATFORM_nxp_t1024)
-    /* NXP T0280 */
+    /* NXP T1024 */
     #define CPU_NUMCORES 2
     #define CORE_E5500
     #define LAW_MAX_ENTRIES 16
@@ -69,16 +69,20 @@
 
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
-    #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
-    #define L2SRAM_SIZE   (256 * 1024)
+    #if 1
+        #define L1_CACHE_ADDR (0xF8F80000) /* L1 as SRAM */
+    #else
+        #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
+        #define L2SRAM_SIZE   (256 * 1024)
+    #endif
     #define ENABLE_INTERRUPTS
 
     #define ENABLE_DDR
 
-    #define FLASH_BASE_ADDR 0xEC000000
+    #define FLASH_BASE_ADDR      0xEC000000
     #define FLASH_BASE_PHYS_HIGH 0x0
-    #define FLASH_LAW_SIZE LAW_SIZE_64MB
-    #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M
+    #define FLASH_LAW_SIZE       LAW_SIZE_64MB
+    #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_64M
 
     #define USE_LONG_JUMP
 
@@ -103,10 +107,10 @@
 
     #define ENABLE_DDR
 
-    #define FLASH_BASE_ADDR 0xE8000000
+    #define FLASH_BASE_ADDR      0xE8000000
     #define FLASH_BASE_PHYS_HIGH 0x0
-    #define FLASH_LAW_SIZE LAW_SIZE_128MB
-    #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M
+    #define FLASH_LAW_SIZE       LAW_SIZE_128MB
+    #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_128M
 
     #define USE_LONG_JUMP
 #else
@@ -150,9 +154,9 @@
 #define L1_CACHE_SZ     (32 * 1024)
 #endif
 
-#ifdef CORE_E500
-    /* PowerPC e500 */
-    /* EREF: 7.5.3.2 - TLB Entry Page Size */
+#if defined(CORE_E500) || defined(CORE_E5500)
+    /* E500CORERM: 2.12.5.2 MAS Register 1 (MAS1)
+     * E5500RM: 2.16.6.2 MAS Register 1 (MAS1) */
     #define BOOKE_PAGESZ_4K    1
     #define BOOKE_PAGESZ_16K   2
     #define BOOKE_PAGESZ_64K   3
@@ -167,6 +171,37 @@
 
     #define MAS1_TSIZE_MASK    0x00000F00
     #define MAS1_TSIZE(x)      (((x) << 8) & MAS1_TSIZE_MASK)
+#elif defined(CORE_E6500)
+    /* E6500RM: 2.13.10.2 MMU Assist 1 (MAS1)
+     * EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
+    #define BOOKE_PAGESZ_4K    2
+    #define BOOKE_PAGESZ_8K    3
+    #define BOOKE_PAGESZ_16K   4
+    #define BOOKE_PAGESZ_32K   5
+    #define BOOKE_PAGESZ_64K   6
+    #define BOOKE_PAGESZ_128K  7
+    #define BOOKE_PAGESZ_256K  8
+    #define BOOKE_PAGESZ_512K  9
+    #define BOOKE_PAGESZ_1M    10
+    #define BOOKE_PAGESZ_2M    11
+    #define BOOKE_PAGESZ_4M    12
+    #define BOOKE_PAGESZ_8M    13
+    #define BOOKE_PAGESZ_16M   14
+    #define BOOKE_PAGESZ_32M   15
+    #define BOOKE_PAGESZ_64M   16
+    #define BOOKE_PAGESZ_128M  17
+    #define BOOKE_PAGESZ_256M  18
+    #define BOOKE_PAGESZ_512M  19
+    #define BOOKE_PAGESZ_1G    20
+    #define BOOKE_PAGESZ_2G    21
+    #define BOOKE_PAGESZ_4G    22
+
+    #define MAS1_TSIZE_MASK    0x00000F80
+    #define MAS1_TSIZE(x)      (((x) << 7) & MAS1_TSIZE_MASK)
+#endif
+
+#ifdef CORE_E500
+    /* PowerPC e500 */
 
     #define CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */
 
@@ -218,36 +253,34 @@
     #define USE_CORENET_INTERFACE
     #define HAS_EMBEDDED_HYPERVISOR /* E.HV Supported */
 
-    /* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
-    #define BOOKE_PAGESZ_4K    2
-    #define BOOKE_PAGESZ_8K    3
-    #define BOOKE_PAGESZ_16K   4
-    #define BOOKE_PAGESZ_32K   5
-    #define BOOKE_PAGESZ_64K   6
-    #define BOOKE_PAGESZ_128K  7
-    #define BOOKE_PAGESZ_256K  8
-    #define BOOKE_PAGESZ_512K  9
-    #define BOOKE_PAGESZ_1M    10
-    #define BOOKE_PAGESZ_2M    11
-    #define BOOKE_PAGESZ_4M    12
-    #define BOOKE_PAGESZ_8M    13
-    #define BOOKE_PAGESZ_16M   14
-    #define BOOKE_PAGESZ_32M   15
-    #define BOOKE_PAGESZ_64M   16
-    #define BOOKE_PAGESZ_128M  17
-    #define BOOKE_PAGESZ_256M  18
-    #define BOOKE_PAGESZ_512M  19
-    #define BOOKE_PAGESZ_1G    20
-    #define BOOKE_PAGESZ_2G    21
-    #define BOOKE_PAGESZ_4G    22
-
-    #define MAS1_TSIZE_MASK    0x00000F80
-    #define MAS1_TSIZE(x)      (((x) << 7) & MAS1_TSIZE_MASK)
-
     #define CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */
 
     /* CoreNet Platform Cache Base */
-    #define CPC_BASE        (CCSRBAR + 0x10000)
+    #define CPC_BASE            (CCSRBAR + 0x10000)
+    /* 8.2 CoreNet Platform Cache (CPC) Memory Map */
+    #define CPCCSR0             (0x000)
+    #define CPCSRCR1            (0x100)
+    #define CPCSRCR0            (0x104)
+    #define CPCHDBCR0           (0xF00)
+
+    #define CPCCSR0_CPCE        (0x80000000 >> 0)
+    #define CPCCSR0_CPCPE       (0x80000000 >> 1)
+    #define CPCCSR0_CPCFI       (0x80000000 >> 10)
+    #define CPCCSR0_CPCLFC      (0x80000000 >> 21)
+    #define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
+
+    #ifdef CORE_E6500
+        #define CPCSRCR0_SRAMSZ_64  (0x1 << 1) /* ways 14-15 */
+        #define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
+        #define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
+    #else /* CORE E5500 */
+        #define CPCSRCR0_SRAMSZ_64  (0x1 << 1) /* ways 6-7 */
+        #define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */
+        #define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 0-7 */
+    #endif
+    #define CPCSRCR0_SRAMEN     (0x1)
+
+    #define CPCHDBCR0_SPEC_DIS  (0x80000000 >> 4)
 
     /* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */
     #define LAWBAR_BASE(n) (0xC00 + (n * 0x10))
@@ -300,7 +333,6 @@
     #define LAW_SIZE_256GB 0x25
     #define LAW_SIZE_512GB 0x26
     #define LAW_SIZE_1TB   0x27
-
 #endif
 
 #ifndef CACHE_LINE_SIZE
@@ -310,6 +342,7 @@
 
 /* MMU Assist Registers
  * E6500RM 2.13.10
+ * E5500RM 2.16.6
  * E500CORERM 2.12.5
  */
 #define MAS0     0x270

diff --git a/hal/nxp_t1024.ld b/hal/nxp_t1024.ld
@@ -13,8 +13,8 @@ MEMORY
 {
     FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
 
-    /* L2 as SRAM - 256KB */
-    RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x40000
+    /* L2 as SRAM - 16KB */
+    RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000
 
     /* DDR - 2GB: Start at 16MB to avoid using 0x0 (NULL) addresses */
     DRAM (rwx) : ORIGIN = 0x1000000, LENGTH = 0x7FFFFFFF - 0x1000000

diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S
@@ -526,26 +526,8 @@ l2_sram_tlb:
                 BOOKE_PAGESZ_256K, 1, r3);
 
 l2_setup_sram:
-        /* 8.2 CoreNet Platform Cache (CPC) Memory Map */
-        #define CPCCSR0             (0x000)
-        #define CPCSRCR1            (0x100)
-        #define CPCSRCR0            (0x104)
-        #define CPCHDBCR0           (0xF00)
-
-        #define CPCCSR0_CPCE        (0x80000000 >> 0)
-        #define CPCCSR0_CPCPE       (0x80000000 >> 1)
-        #define CPCCSR0_CPCFI       (0x80000000 >> 10)
-        #define CPCCSR0_CPCLFC      (0x80000000 >> 21)
-        #define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
-
-        #define CPCSRCR0_SRAMSZ_64  (0x1 << 1) /* ways 14-15 */
-        #define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
-        #define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
-        #define CPCSRCR0_SRAMEN     (0x1)
-
-        #define CPCHDBCR0_SPEC_DIS  (0x80000000 >> 4)
-
-        /* T2080RM: 8.4.2.2 Enabling the CPC after Power-On Reset */
+        /* T2080RM: 8.4.2.2 or T1024RM 13.4.2.2
+         * Enabling the CPC after Power-On Reset */
         /* R1 = CPC base */
         lis     r1, CPC_BASE@h
         ori     r1, r1, CPC_BASE@l
@@ -567,12 +549,12 @@ l2_setup_sram:
         isync
         stw     r0, CPCCSR0(r1)
         mbar
-#endif /* L2SRAM_ADDR */
 
         /* Disable speculation */
         lwz     r0, CPCHDBCR0(r1)
         oris    r0, r0, CPCHDBCR0_SPEC_DIS@h
         stw     r0, CPCHDBCR0(r1)
+#endif /* L2SRAM_ADDR */
 #endif /* CORE_E5500 || CORE_E6500 */
 
 #if defined(CORE_E6500) /* --- L2 E6500 --- */
@@ -638,8 +620,8 @@ l2_poll_invclear:
         isync
         sync
 
-        /* enable L2 with parity */
-        lis     r4, (L2CSR0_L2E | L2CSR0_L2PE)@h
+        /* enable L2 with no parity */
+        lis     r4, (L2CSR0_L2E)@h
         sync
         isync
         mtspr   L2CSR0, r4