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Progress with DDR and CPLD.
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@dgarske
dgarske committed Sep 21, 2023
1 parent d50de1c commit ab179fd
Showing 1 changed file with 105 additions and 55 deletions.
160 changes: 105 additions & 55 deletions hal/nxp_t1024.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,15 +36,17 @@

#define ENABLE_DDR
#define ENABLE_IFC
#define ENABLE_CPLD
//#define ENABLE_QE /* QUICC Engine */
//#define ENABLE_MP /* multi-core support */
#if defined(WOLFBOOT_TPM) || defined(TEST_TPM)
#define ENABLE_ESPI /* SPI for TPM */
#endif
#if 0
#define ENABLE_CPLD
#endif

#define USE_ERRATA_DDRA008378
#define USE_ERRATA_DDRA008109
#define USE_ERRATA_DDRA009663
#define USE_ERRATA_DDRA009942

#if defined(ENABLE_DDR) && defined(TEST_DDR)
static int test_ddr(void);
Expand Down Expand Up @@ -263,26 +265,34 @@ enum ifc_amask_sizes {
#define CPLD_BASE 0xFFDF0000
#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE)

#define CPLD_SPARE 0x00
#define CPLD_SATA_MUX_SEL 0x02
#define CPLD_BANK_SEL 0x04
#define CPLD_FW_REV 0x06
#define CPLD_TTL_RW 0x08
#define CPLD_TTL_LPBK 0x0A
#define CPLD_TTL_DATA 0x0C
#define CPLD_PROC_STATUS 0x0E /* write 1 to enable proc reset function, reset default value is 0 */
#define CPLD_FPGA_RDY 0x10 /* read only when reg read 0x0DB1 then fpga is ready */
#define CPLD_PCIE_SW_RESET 0x12 /* write 1 to reset the PCIe switch */
#define CPLD_WR_TTL_INT_EN 0x14
#define CPLD_WR_TTL_INT_DIR 0x16
#define CPLD_INT_STAT 0x18
#define CPLD_WR_TEMP_ALM_OVRD 0x1A /* write 0 to enable temp shutdown. reset default value is 1 */
#define CPLD_PWR_DWN_CMD 0x1C
#define CPLD_TEMP_ALM_INT_STAT 0x1E
#define CPLD_WR_TEMP_ALM_INT_EN 0x20

#define CPLD_FLASH_BANK_0 0x00
#define CPLD_FLASH_BANK_1 0x01
#define CPLD_VER 0x00 /* CPLD Major Revision Register */
#define CPLD_VER_SUB 0x01 /* CPLD Minor Revision Register */
#define HW_VER 0x02 /* Hardware Revision Register */
#define SW_VER 0x03 /* Software Revision register */
#define RESET_CTL1 0x10 /* Reset control Register1 */
#define RESET_CTL2 0x11 /* Reset control Register2 */
#define INT_STATUS 0x12 /* Interrupt status Register */
#define FLASH_CSR 0x13 /* Flash control and status register */
#define FAN_CTL_STATUS 0x14 /* Fan control and status register */
#define LED_CTL_STATUS 0x15 /* LED control and status register */
#define SFP_CTL_STATUS 0x16 /* SFP control and status register */
#define MISC_CTL_STATUS 0x17 /* Miscellanies ctrl & status register*/
#define BOOT_OVERRIDE 0x18 /* Boot override register */
#define BOOT_CONFIG1 0x19 /* Boot config override register*/
#define BOOT_CONFIG2 0x1A /* Boot config override register*/

#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80

#define CPLD_PCIE_SGMII_MUX 0x80
#define CPLD_OVERRIDE_BOOT_EN 0x01
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */

#define CPLD_DATA(n) ((volatile uint8_t*)(CPLD_BASE + n))

Expand Down Expand Up @@ -312,10 +322,12 @@ enum ifc_amask_sizes {

#define DDR_SDRAM_MODE_VAL 0x01010215
#define DDR_SDRAM_MODE_2_VAL 0x00000000
#define DDR_SDRAM_MODE_9_VAL 0x00000500 /* Extended SDRAM mode 5 */
#define DDR_SDRAM_MODE_10_VAL 0x04000000 /* Extended SDRAM mode 7 */
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
#define DDR_SDRAM_MD_CNTL_VAL 0x03001000

#define DDR_SDRAM_CFG_VAL 0xE5200000
#define DDR_SDRAM_CFG_VAL 0xE5200000 /* DDR4 w/ECC */
#define DDR_SDRAM_CFG_2_VAL 0x00401040

#define DDR_SDRAM_INTERVAL_VAL 0x18600618
Expand Down Expand Up @@ -345,6 +357,7 @@ enum ifc_amask_sizes {
#define DDR_CS_CONFIG_2(n) ((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */
#define DDR_SDRAM_CFG ((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */
#define DDR_SDRAM_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */
#define DDR_SDRAM_CFG_3 ((volatile uint32_t*)(DDR_BASE + 0x260)) /* DDR SDRAM control configuration 3 */
#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
#define DDR_INIT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */
#define DDR_INIT_EXT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */
Expand All @@ -365,6 +378,10 @@ enum ifc_amask_sizes {
#define DDR_SR_CNTR ((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */
#define DDR_SDRAM_RCW_1 ((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */
#define DDR_SDRAM_RCW_2 ((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */
#define DDR_SDRAM_RCW_3 ((volatile uint32_t*)(DDR_BASE + 0x1A0)) /* DDR Register Control Word 3 */
#define DDR_SDRAM_RCW_4 ((volatile uint32_t*)(DDR_BASE + 0x1A4)) /* DDR Register Control Word 4 */
#define DDR_SDRAM_RCW_5 ((volatile uint32_t*)(DDR_BASE + 0x1A8)) /* DDR Register Control Word 5 */
#define DDR_SDRAM_RCW_6 ((volatile uint32_t*)(DDR_BASE + 0x1AC)) /* DDR Register Control Word 6 */
#define DDR_DDRCDR_1 ((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */
#define DDR_DDRCDR_2 ((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */
#define DDR_DDRDSR_1 ((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */
Expand All @@ -380,18 +397,29 @@ enum ifc_amask_sizes {
#define DDR_SDRAM_MODE_6 ((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */
#define DDR_SDRAM_MODE_7 ((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
#define DDR_SDRAM_MODE_8 ((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
#define DDR_SDRAM_MODE_9 ((volatile uint32_t*)(DDR_BASE + 0x220)) /* DDR SDRAM mode configuration 9 */
#define DDR_SDRAM_MODE_10 ((volatile uint32_t*)(DDR_BASE + 0x224)) /* DDR SDRAM mode configuration 10 */
#define DDR_SDRAM_MD_CNTL ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */

#define DDR_DEBUG_9 ((volatile uint32_t*)(DDR_BASE + 0xF20))
#define DDR_DEBUG_10 ((volatile uint32_t*)(DDR_BASE + 0xF24))
#define DDR_DEBUG_11 ((volatile uint32_t*)(DDR_BASE + 0xF28))
#define DDR_DEBUG_12 ((volatile uint32_t*)(DDR_BASE + 0xF2C))
#define DDR_DEBUG_13 ((volatile uint32_t*)(DDR_BASE + 0xF30))
#define DDR_DEBUG_14 ((volatile uint32_t*)(DDR_BASE + 0xF34))
#define DDR_DEBUG_19 ((volatile uint32_t*)(DDR_BASE + 0xF48))
#define DDR_DEBUG_29 ((volatile uint32_t*)(DDR_BASE + 0xF70))

#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
#define DDR_SDRAM_CFG_ECC_EN 0x20000000
#define DDR_SDRAM_CFG_32_BE 0x00080000
#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
#define DDR_SDRAM_CFG_HSE 0x00000008
#define DDR_SDRAM_CFG_BI 0x00000001 /* Bypass initialization */

#define DDR_SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define DDR_SDRAM_CFG_SDRAM_TYPE(n) (((n) & 0x7) << 24)
#define DDR_SDRAM_TYPE_DDR4 5
#define DDR_SDRAM_INTERVAL_BSTOPRE 0x3FFF


Expand Down Expand Up @@ -667,6 +695,10 @@ static void hal_ddr_init(void)
/* Map LAW for DDR */
set_law(15, DDR_ADDRESS, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB);

/* Set early for clock / pin */
set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL);
set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL);

/* Setup DDR CS (chip select) bounds */
set32(DDR_CS_BNDS(0), DDR_CS0_BNDS_VAL);
set32(DDR_CS_CONFIG(0), DDR_CS0_CONFIG_VAL);
Expand All @@ -682,14 +714,17 @@ static void hal_ddr_init(void)
set32(DDR_CS_CONFIG_2(3), DDR_CS_CONFIG_2_VAL);

/* DDR SDRAM timing configuration */
set32(DDR_TIMING_CFG_3, DDR_TIMING_CFG_3_VAL);
set32(DDR_TIMING_CFG_0, DDR_TIMING_CFG_0_VAL);
set32(DDR_TIMING_CFG_1, DDR_TIMING_CFG_1_VAL);
set32(DDR_TIMING_CFG_2, DDR_TIMING_CFG_2_VAL);
set32(DDR_TIMING_CFG_3, DDR_TIMING_CFG_3_VAL);
set32(DDR_TIMING_CFG_4, DDR_TIMING_CFG_4_VAL);
set32(DDR_TIMING_CFG_5, DDR_TIMING_CFG_5_VAL);
set32(DDR_TIMING_CFG_8, DDR_TIMING_CFG_8_VAL);

set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL);
set32(DDR_SDRAM_CFG_3, 0);

/* DDR SDRAM mode configuration */
set32(DDR_SDRAM_MODE, DDR_SDRAM_MODE_VAL);
set32(DDR_SDRAM_MODE_2, DDR_SDRAM_MODE_2_VAL);
Expand All @@ -699,39 +734,55 @@ static void hal_ddr_init(void)
set32(DDR_SDRAM_MODE_6, DDR_SDRAM_MODE_3_8_VAL);
set32(DDR_SDRAM_MODE_7, DDR_SDRAM_MODE_3_8_VAL);
set32(DDR_SDRAM_MODE_8, DDR_SDRAM_MODE_3_8_VAL);
set32(DDR_SDRAM_MODE_9, DDR_SDRAM_MODE_9_VAL);
set32(DDR_SDRAM_MODE_10, DDR_SDRAM_MODE_10_VAL);
set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL);

/* DDR Configuration */
#ifdef USE_ERRATA_DDRA009663
/* Errata A-009663 - DRAM VRef training (do not set precharge interval till after enable) */
set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL & ~DDR_SDRAM_INTERVAL_BSTOPRE);
set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL);
#else
set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL);
#endif
set32(DDR_DATA_INIT, DDR_DATA_INIT_VAL);
set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL);
set32(DDR_WRLVL_CNTL, DDR_WRLVL_CNTL_VAL);
set32(DDR_WRLVL_CNTL_2, DDR_WRLVL_CNTL_2_VAL);
set32(DDR_WRLVL_CNTL_3, DDR_WRLVL_CNTL_3_VAL);
set32(DDR_SR_CNTR, 0);
set32(DDR_SDRAM_RCW_1, 0);
set32(DDR_SDRAM_RCW_2, 0);
set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL);
set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL);
set32(DDR_SDRAM_RCW_3, 0);
set32(DDR_SDRAM_RCW_4, 0);
set32(DDR_SDRAM_RCW_5, 0);
set32(DDR_SDRAM_RCW_6, 0);
set32(DDR_SDRAM_CFG_2, DDR_SDRAM_CFG_2_VAL);
set32(DDR_INIT_ADDR, 0);
set32(DDR_INIT_EXT_ADDR, 0);
set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL);
set32(DDR_ERR_DISABLE, 0);
set32(DDR_ERR_INT_EN, DDR_ERR_INT_EN_VAL);
set32(DDR_ERR_SBE, DDR_ERR_SBE_VAL);

reg = (get32(DDR_DEBUG_29) & 0xFFFFFF00);
set32(DDR_DEBUG_29, reg | 0x43);

/* Set values, but do not enable the DDR yet */
set32(DDR_SDRAM_CFG, (DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN));
set32(DDR_SDRAM_CFG, DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");

/* busy wait for ~500us */
udelay(500);
asm volatile("sync;isync");

#ifdef USE_ERRATA_DDRA008378
/* Errata A-008378: training in DDR4 mode */
/* write to DEBUG_29[8:11] a value of 4'b1001 before controller is enabled */
reg = get32(DDR_DEBUG_29);
reg |= (0x9 << 20);
set32(DDR_DEBUG_29, reg);

#endif
#ifdef USE_ERRATA_DDRA008109
/* Errata A-008109: Memory controller could fail to complete initialization */
reg = get32(DDR_SDRAM_CFG_2);
reg |= 0x800; /* set DDR_SLOW */
Expand All @@ -740,16 +791,14 @@ static void hal_ddr_init(void)
reg |= 0x2;
set32(DDR_DEBUG_19, reg);
set32(DDR_DEBUG_29, 0x30000000);

#endif
#ifdef USE_ERRATA_DDRA009942
/* Errata A-009942: DDR controller can train to non-optimal setting */
reg = get32(DDR_DEBUG_29);
reg &= ~0xFF0FFF00;
reg |= 0x0070006F; /* DDR-1400/1500/1600 */
reg |= 0x0070006F; /* CPO calculated */
set32(DDR_DEBUG_29, reg);

/* busy wait for ~500us */
udelay(500);
asm volatile("sync;isync");
#endif

/* Enable controller */
reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
Expand All @@ -762,8 +811,10 @@ static void hal_ddr_init(void)
udelay(10000);
}

#ifdef USE_ERRATA_DDRA009663
/* Errata A-009663 - Write real precharge interval */
set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL);
#endif

/* DDR - TBL=1, Entry 12/13 */
set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS,
Expand Down Expand Up @@ -809,24 +860,24 @@ static void hal_cpld_init(void)
uint32_t fw;
#endif
/* CPLD IFC Timing Parameters */
set32(IFC_FTIM0(3), (IFC_FTIM0_GPCM_TACSE(16) |
IFC_FTIM0_GPCM_TEADC(16) |
IFC_FTIM0_GPCM_TEAHC(16)));
set32(IFC_FTIM1(3), (IFC_FTIM1_GPCM_TACO(16) |
set32(IFC_FTIM0(2), (IFC_FTIM0_GPCM_TACSE(14) |
IFC_FTIM0_GPCM_TEADC(14) |
IFC_FTIM0_GPCM_TEAHC(14)));
set32(IFC_FTIM1(2), (IFC_FTIM1_GPCM_TACO(14) |
IFC_FTIM1_GPCM_TRAD(31)));
set32(IFC_FTIM2(3), (IFC_FTIM2_GPCM_TCS(16) |
set32(IFC_FTIM2(2), (IFC_FTIM2_GPCM_TCS(14) |
IFC_FTIM2_GPCM_TCH(8) |
IFC_FTIM2_GPCM_TWP(31)));
set32(IFC_FTIM3(3), 0);
set32(IFC_FTIM3(2), 0);

/* CPLD IFC Definitions (CS3) */
set32(IFC_CSPR_EXT(3), (0xF));
set32(IFC_CSPR(3), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
IFC_CSPR_PORT_SIZE_16 |
/* CPLD IFC Definitions (CS2) */
set32(IFC_CSPR_EXT(2), GET_PHYS_HIGH(CPLD_BASE_PHYS));
set32(IFC_CSPR(2), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
IFC_CSPR_PORT_SIZE_8 |
IFC_CSPR_MSEL_GPCM |
IFC_CSPR_V));
set32(IFC_AMASK(3), IFC_AMASK_64KB);
set32(IFC_CSOR(3), 0);
set32(IFC_AMASK(2), IFC_AMASK_64KB);
set32(IFC_CSOR(2), 0);

/* IFC - CPLD */
set_law(2, GET_PHYS_HIGH(CPLD_BASE_PHYS), CPLD_BASE,
Expand All @@ -837,12 +888,11 @@ static void hal_cpld_init(void)
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, BOOKE_PAGESZ_4K, 1);

set8(CPLD_DATA(CPLD_PROC_STATUS), 1); /* Enable proc reset */
set8(CPLD_DATA(CPLD_WR_TEMP_ALM_OVRD), 0); /* Enable temp alarm */

#ifdef DEBUG_UART
fw = get8(CPLD_DATA(CPLD_FW_REV));
wolfBoot_printf("CPLD FW Rev: 0x%x\n", fw);
fw = get8(CPLD_DATA(HW_VER));
wolfBoot_printf("CPLD HW Rev: 0x%x\n", fw);
fw = get8(CPLD_DATA(SW_VER));
wolfBoot_printf("CPLD SW Rev: 0x%x\n", fw);
#endif
#endif /* ENABLE_CPLD */
}
Expand Down

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