target/riscv/pmp: Fix address matching, granularity and debug

- Add tracing to CSR reads and writes to pmpcfg and pmpaddr.
- Rename pmp_hart_has_priv to pmp_has_access.
- Simplify address matching rules and add tracing.
- Mask addresss writes so granularity can be detected.
- Remove redundant debugging statements

target/riscv/cpu_helper.c

@@ -452,6 +452,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
 #if !defined(CONFIG_USER_ONLY)
     hwaddr pa = 0;
     int prot;
+    target_ulong tlb_entry_size = TARGET_PAGE_SIZE;
 #endif
     int ret = TRANSLATE_FAIL;
 
@@ -464,14 +465,14 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU,
             "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
              " prot %d\n", __func__, address, ret, pa, prot);
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-        !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) {
-        ret = TRANSLATE_FAIL;
+    if (ret == TRANSLATE_SUCCESS && riscv_feature(env, RISCV_FEATURE_PMP)) {
+        ret = pmp_has_access(env, pa, rw, TARGET_PAGE_SIZE, &tlb_entry_size) ?
+              TRANSLATE_SUCCESS : TRANSLATE_FAIL;
     }
     if (ret == TRANSLATE_SUCCESS) {
         tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
-                     prot, mmu_idx, TARGET_PAGE_SIZE);
-    } else if (ret == TRANSLATE_FAIL) {
+                     prot, mmu_idx, tlb_entry_size);
+    } else {
         raise_mmu_exception(env, address, rw);
     }
 #else