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Issues: riscvarchive/riscv-qemu
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single float arith instructions don't produce NaN boxed output.
#174
opened Oct 18, 2018 by
jim-wilson
si does not stop to next instruction if current instruction is csrr/csrw in remote debug
#170
opened Sep 27, 2018 by
lbmeng
Read/write of CSR registers via GDB doesn't work
qemu-for-testing
Fixed in the qemu-for-testing branch
#156
opened Jul 25, 2018 by
sebhub
Hello-world user space not working in qemu and current gnu toolchain ?
#148
opened Jun 28, 2018 by
anon63github
0x00000000
decodes to mv s0, sp
qemu-for-upstream
#147
opened Jun 13, 2018 by
palmer-dabbelt
User mode can access address which has a page table entry with U=0.
#146
opened May 22, 2018 by
LuChengTHU
Add RVE register bounds checks to Base ISA ('I'/'E') in translate.c
#144
opened May 17, 2018 by
michaeljclark
Populate mtval with instruction bytes on illegal instruction traps
#141
opened May 8, 2018 by
michaeljclark
qemu-system-riscv32 store doesn't modify the memory during a
sw ra, 12(sp)
#137
opened Apr 27, 2018 by
vsiles
linux-user riscv32 stat structure doesn't match glibc/musl
qemu-for-upstream
Fixed in the qemu-for-upstream branch
#135
opened Apr 20, 2018 by
michaeljclark
WFI doesn't return when a IPI is issued
qemu-for-upstream
Fixed in the qemu-for-upstream branch
#132
opened Apr 13, 2018 by
atishp04
Don't generate exceptions for CSR access in gdbstub.c
qemu-for-upstream
Fixed in the qemu-for-upstream branch
#127
opened Apr 4, 2018 by
michaeljclark
Generate illegal instruction traps for s* CSR accesses if misa.S is not set
qemu-for-upstream
Fixed in the qemu-for-upstream branch
#126
opened Apr 4, 2018 by
michaeljclark
Priv 1.10 should use *tval instead of *badaddr
qemu-for-upstream
Fixed in the qemu-for-upstream branch
#125
opened Apr 1, 2018 by
msuozzo
Mask mie/mip fields depending on whether S mode is enabled (misa.S)
#114
opened Mar 5, 2018 by
michaeljclark
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