SiFive CLIC (Core Level Interrupt Controller) test-beta1

- Implements draft clic-spec (20180728)
  - Implements non-vectored mode and vectored mode
  - Implements mode+level+priority configuration
  - Implements mode+level+priority preemption model
  - Seperated M-mode (mtvec) and S-mode (stvec) delivery
  - CLIC supports backwards compatible CLINT mode for
    legacy interrupts using MIE/MIP,SIE/SIP (irq < 16)
    depending on mtvec (MTI,MSI) and stvec (STI,SSI)
  - CLINT mode supports S-mode stimecmp{h} and ssip{h}

- QEMU CLINT/CLIC Test Cases
  - https://github.com/michaeljclark/qemu-riscv-tests

- Adds two experimental machines
  - SiFive Freedom E-Series with CLIC
    - Implements M-mode CLINT/CLIC config memory map
    - Parameters
      - CLICINTBITS=4
      - CLICCFGMBITS=0
      - CLICCFGLBITS=4
    - Invocation
      - qemu-system-riscv{32,64} -machine sifive_ex
  - SiFive Freedom U-Series with CLIC
    - Implements M-mode and S-mode CLINT/CLIC memory map
    - Parameters
      - CLICINTBITS=8
      - CLICCFGMBITS=2
      - CLICCFGLBITS=4
    - Invocation
      - qemu-system-riscv{32,64} -machine sifive_ux

- CLIC combined CLINT/CLIC memory map
  - M-Mode CLINT = 0x02000000
    - msip       = 0x02000000 + hartid * 4
    - mtimecmp   = 0x02004000 + hartid * 4
    - mtime      = 0x0200bff8
  - S-Mode CLINT = 0x02020000
  - M-mode CLIC  = 0x02080000
    - clicintip  = 0x02080000 + hartid * 0x1000 + 0x000
    - clicintie  = 0x02080000 + hartid * 0x1000 + 0x400
    - clicintcfg = 0x02080000 + hartid * 0x1000 + 0x800
    - cliccfg    = 0x02080000 + hartid * 0x1000 + 0xc00
  - S-Mode CLIC  = 0x020c0000
    - clicintip  = 0x020c0000 + hartid * 0x1000 + 0x000
    - clicintie  = 0x020c0000 + hartid * 0x1000 + 0x400
    - clicintcfg = 0x020c0000 + hartid * 0x1000 + 0x800

- Adds CLIC interrupt tracing (`-d trace:riscv_trap,...`)
  - riscv_trap         # existing core interrupt tracing
  - sifive_clic_cfg    # CLIC global configuration
  - sifive_clic_intcfg # CLIC interrupt configuration
  - sifive_clic_intie  # CliC interrupt enable
  - sifive_clic_intip  # CLIC interrupt pending
  - sifive_clic_irq    # CLIC irq entry

- Notes / Limitations
  - Enforces clicintcfg writes based on cliccfg and mode
  - Reads/writes to intcfg/intie/intip in lower mode MMIO
    apetures are currently allowed. Access checks need to
    be added to suppress writes and hardwire read reults to
    zero for any entries that where mode < clicintcfg.mode
  - Interrupts pending bits are writable by software.
    Edge/Level configuration needs to be added to control
    software access to interrupt pending bits
  - Selective vectoring in non-vectored mode is unimplemented
  - PLIC is currently not routed via the CLIC however pending
    bits can be written by software to test pre-emption.
  - mnxti/snxti sets mstatus flags but returns 0 (slow path).
    The CLIC state is currenetly not accessible from target/riscv
    as cpu implementations can't include anything from include/hw
    so the CLIC state needs to be in a CPU accessible structure.
  - Potential race condition if an interrupt is posted
    before the CPU has received and processed an outstanding
    interrupt due to env->exccode being overwritten.
    Needs changes to the interface from the CLIC so that the
    CPU interrupt handler pulls the highest priority interrupt
    from the CLIC at the time it is woken up. This requires the
    CLIC state to be accessible from the CPU similarly to mnxti
  - CPU core changes are relatively intrusive. The CPU interrupt
    handling requires some abstraction/hooks for a more modular
    CLIC implementation. CLIC state needs to be attached to
    the CPU, and accessible to the MMIO device with hooks in
    riscv_cpu_exec_interrupt and riscv_cpu_do_interrupt

Changes since v0

- Fix array index calculation in sifive_clic_realize
- Raise CLIC_LEVEL_BITS to 8 and fix assertion
- Move CLIC parameterization constants to its header

Makefile.objs

@@ -228,6 +228,7 @@ trace-events-subdirs += hw/nvram
 trace-events-subdirs += hw/pci
 trace-events-subdirs += hw/pci-host
 trace-events-subdirs += hw/ppc
+trace-events-subdirs += hw/riscv
 trace-events-subdirs += hw/rdma
 trace-events-subdirs += hw/rdma/vmw
 trace-events-subdirs += hw/s390x

hw/riscv/Makefile.objs

@@ -2,6 +2,7 @@ obj-y += boot.o
 obj-y += riscv_htif.o
 obj-y += riscv_hart.o
 obj-y += sifive_e.o
+obj-y += sifive_clic.o
 obj-y += sifive_clint.o
 obj-y += sifive_prci.o
 obj-y += sifive_plic.o