target/riscv: use cacheable read/write function to handle DCSR

[lz-bro]

Avoid cache and memory inconsistencies on DCSR
Change-Id: c99efe3

[JanMatCodasip]

Hi @lz-bro, thank you for catching the bug.

I recommend a different way of fixing it:

The functions riscv013_set_register and riscv013_get_register should remain low-level and not deal with the register cache. That means they should only call register_read_direct() and register_write_direct(), not the higher-level cache aware functions riscv_get_register() and riscv_set_register().

My proposal is to move the rid checks to riscv_get_register():

int riscv_get_register(struct target *target, riscv_reg_t *value,
		enum gdb_regno regid)
{
	RISCV_INFO(r);
	assert(r->get_register);

	keep_alive();

	/* Handle virtual registers - moved code */

	if (rid == GDB_REGNO_PC) {
		return riscv_get_register(target, value, GDB_REGNO_DPC);
	} else if (rid == GDB_REGNO_PRIV) {
		uint64_t dcsr;
		if (riscv_get_register(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
			return ERROR_FAIL;
		/*...*/
	}
	
	/* Handle read from the actual register - existing code */
	
	if (!target->reg_cache) {
		assert(!target_was_examined(target));
		LOG_TARGET_DEBUG(target, "No cache, reading %s from target",
				gdb_regno_name(regid));
		return r->get_register(target, value, regid);
	}

	struct reg *reg = get_reg_cache_entry(target, regid);
	/* ... */
}

Analogously for riscv_set_register().

@timsifive Does this make sense to you, too? Or am I overreaching on this one?

[lz-bro]

@JanMatCodasip Thank you for your suggestion, I will modify it later

[timsifive]

It's not clear to me what bug this is fixing. Was there a discussion somewhere else?

Also, it's failing several of the automated build actions (which I just enabled for you). Please take a look.

[timsifive]

Looks good. Cleans up the code and fixes a bug. :-)

[JanMatCodasip]

LGTM. Thank you.

[JanMatCodasip]

@lz-bro Please note that there is a conflict that should be resolved prior to the merge.

Thanks.

[lz-bro]

@lz-bro Please note that there is a conflict that should be resolved prior to the merge.

Thanks.
I have resolved the conflict，thank you.

[en-sc]

The move of priv read/write from version-specific part causes priv.v to be read incorrectly for 0.11 targets.
The issue is: dcsr[5] is dcsr.v for the current spec, but it is dcsr.debugint for 0.11
Will prepare a patch with a fix.

[en-sc]

Will prepare a patch with a fix.

#997