target/riscv: use cacheable read/write function to handle DCSR

Signed-off-by: liangzhen <[email protected]>
riscv-collab · Sep 21, 2023 · c99efe3 · c99efe3
1 parent 2427f58
commit c99efe3
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
@@ -4706,7 +4706,7 @@ static int riscv013_get_register(struct target *target,
 	} else if (rid == GDB_REGNO_PRIV) {
 		uint64_t dcsr;
 		/* TODO: move this into riscv.c. */
-		if (register_read_direct(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
+		if (riscv_get_register(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
 			return ERROR_FAIL;
 		*value = set_field(0, VIRT_PRIV_V, get_field(dcsr, CSR_DCSR_V));
 		*value = set_field(*value, VIRT_PRIV_PRV, get_field(dcsr, CSR_DCSR_PRV));
@@ -4736,11 +4736,11 @@ static int riscv013_set_register(struct target *target, enum gdb_regno rid,
 	} else if (rid == GDB_REGNO_PRIV) {
 		riscv_reg_t dcsr;
 
-		if (register_read_direct(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
+		if (riscv_get_register(target, &dcsr, GDB_REGNO_DCSR) != ERROR_OK)
 			return ERROR_FAIL;
 		dcsr = set_field(dcsr, CSR_DCSR_PRV, get_field(value, VIRT_PRIV_PRV));
 		dcsr = set_field(dcsr, CSR_DCSR_V, get_field(value, VIRT_PRIV_V));
-		return register_write_direct(target, GDB_REGNO_DCSR, dcsr);
+		return riscv_set_register(target, GDB_REGNO_DCSR, dcsr);
 	} else {
 		return register_write_direct(target, rid, value);
 	}
@@ -4951,7 +4951,7 @@ static int riscv013_on_step(struct target *target)
 static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
 {
 	riscv_reg_t dcsr;
-	int result = register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
+	int result = riscv_get_register(target, &dcsr, GDB_REGNO_DCSR);
 	if (result != ERROR_OK)
 		return RISCV_HALT_UNKNOWN;