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Allow reset connection in SCM if FPGA target is exported. #13

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Allow reset connection in SCM if FPGA target is exported.

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Closed

Allow reset connection in SCM if FPGA target is exported. #13

Allow reset connection in SCM if FPGA target is exported.
672d2d5
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GitHub Actions / verible-verilog-lint succeeded Jun 9, 2024 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (0)
Filtered Findings (4)

src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv|598 col 26| Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv|611 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv|616 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv|631 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

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