Allow reset connection in SCM if FPGA target is exported.

.github/workflows/lint.yml

@@ -23,6 +23,9 @@ jobs:
           paths: |
             ./src
             ./test
+          exclude_paths: |
+            ./src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
+            ./src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
           github_token: ${{ secrets.GITHUB_TOKEN }}
           fail_on_error: true
           reviewdog_reporter: github-check

Bender.yml

@@ -16,6 +16,7 @@ dependencies:
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 }
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1 }
   scm:                { git: "https://github.com/pulp-platform/scm.git",                version: 1.1.0 }
+  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -24,6 +25,7 @@ sources:
   # Level 0
   - src/snitch_icache_pkg.sv
   - src/riscv_instr_branch.sv
+  - src/multi_accept_rr_arb.sv
   # Level 1
   - src/snitch_axi_to_cache.sv
   - src/snitch_icache_l0.sv
@@ -36,6 +38,16 @@ sources:
   # Level 3
   - src/snitch_icache.sv
   - src/snitch_read_only_cache.sv
+  # Level 4
+  - src/pulp_icache_wrap.sv
+  - files: # ctrl_unit
+    - src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
+    - src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
+    - src/ctrl_unit/cluster_icache_ctrl_unit.sv
+  - files: # ctrl_unit
+    - src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_pkg.sv
+    - src/ctrl_unit/cluster_icache_ctrl_perfctr_reg_top.sv
+    - src/ctrl_unit/cluster_icache_ctrl_perfctr_unit.sv
   - target: test
     files:
       - test/snitch_icache_l0_tb.sv

Makefile

@@ -9,13 +9,26 @@ VLOG_FLAGS += -svinputport=compat
 VLOG_FLAGS += -suppress 2583
 VLOG_FLAGS += +cover=sbecft
 
+CTRL_UNIT_DIR = src/ctrl_unit
+CTRL_UNIT = $(CTRL_UNIT_DIR)/cluster_icache_ctrl
+CTRL_UNIT_PERF = $(CTRL_UNIT_DIR)/cluster_icache_ctrl_perfctr
+
 Bender.lock:
 	$(BENDER) update
 
 .bender:
 	$(BENDER) checkout
 
-compile.tcl: .bender
+.PHONY: gen_hw
+gen_hw: .bender $(CTRL_UNIT)_reg_top.sv $(CTRL_UNIT_PERF)_reg_top.sv
+
+$(CTRL_UNIT)_reg_top.sv: .bender $(CTRL_UNIT).hjson
+	python $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py $(CTRL_UNIT).hjson -t $(CTRL_UNIT_DIR) -r
+
+$(CTRL_UNIT_PERF)_reg_top.sv: .bender $(CTRL_UNIT_PERF).hjson
+	python $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py $(CTRL_UNIT_PERF).hjson -t $(CTRL_UNIT_DIR) -r
+
+compile.tcl: .bender Bender.yml Bender.lock
 	$(BENDER) script vsim -t test \
     --vlog-arg="$(VLOG_FLAGS)" \
     > compile.tcl

src/ctrl_unit/cluster_icache_ctrl.hjson

@@ -0,0 +1,146 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+{
+  name: "cluster_icache_ctrl",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  param_list: [
+    { name: "NumCores",
+      desc: "Number of cores",
+      default: "8"
+    },
+    { name: "NumL0Events",
+      desc: "Number of L0 events",
+      default: "5"
+    },
+    { name: "NumL1Events",
+      desc: "Number of L1 events",
+      default: "6"
+    },
+    { name: "NumAvailableCounters",
+      desc: "Number of available counters",
+      default: "46" // NumL1Events + NumCores * NumL0Events
+    },
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "enable",
+      desc: "",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { name: "flush",
+      desc: "Flush all levels of the cache",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwqe: "true",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "flush",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "flush_l1_only",
+      desc: "not yet functional",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          name: "flush",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "sel_flush_icache",
+      desc: "flush specified L0 banks (and currently the complete L1)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "NumCores-1:0",
+          name: "flush",
+          desc: "",
+          resval: 0x0000_0000
+        }
+      ]
+    },
+    { name: "clear_counters",
+      desc: "Clear all performance counters",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwqe: "true",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "clear",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "enable_counters",
+      desc: "Enable performance counters",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { skipto: "0x1C" },
+    { name: "enable_prefetch",
+      desc: "Enable prefetching",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { multireg: {
+        name: "counters",
+        desc: "Performance counters",
+        count: "NumAvailableCounters",
+        cname: "id",
+        swaccess: "rw0c",
+        hwaccess: "hrw",
+        fields: [
+          { bits: "31:0",
+            name: "counter",
+            desc: "",
+            resval: 0x0000_0000
+          }
+        ]
+      }
+    },
+  ],
+}

src/ctrl_unit/cluster_icache_ctrl_perfctr.hjson

@@ -0,0 +1,146 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+{
+  name: "cluster_icache_ctrl_perfctr",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  param_list: [
+    { name: "NumCores",
+      desc: "Number of cores",
+      default: "8"
+    },
+    { name: "NumL0Events",
+      desc: "Number of L0 events",
+      default: "5" // Use performance counters for L0 events
+    },
+    { name: "NumL1Events",
+      desc: "Number of L1 events",
+      default: "6"
+    },
+    { name: "NumAvailableCounters",
+      desc: "Number of available counters",
+      default: "6" // NumL1Events
+    },
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "enable",
+      desc: "",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { name: "flush",
+      desc: "Flush all levels of the cache",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwqe: "true",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "flush",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "flush_l1_only",
+      desc: "not yet functional",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          name: "flush",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "sel_flush_icache",
+      desc: "flush specified L0 banks (and currently the complete L1)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "NumCores-1:0",
+          name: "flush",
+          desc: "",
+          resval: 0x0000_0000
+        }
+      ]
+    },
+    { name: "clear_counters",
+      desc: "Clear all performance counters",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwqe: "true",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "clear",
+          desc: "",
+          resval: 0x0
+        }
+      ]
+    },
+    { name: "enable_counters",
+      desc: "Enable performance counters",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { skipto: "0x1C" },
+    { name: "enable_prefetch",
+      desc: "Enable prefetching",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "",
+          resval: 0x1
+        }
+      ]
+    },
+    { multireg: {
+        name: "counters",
+        desc: "Performance counters",
+        count: "NumAvailableCounters",
+        cname: "id",
+        swaccess: "rw0c",
+        hwaccess: "hrw",
+        fields: [
+          { bits: "31:0",
+            name: "counter",
+            desc: "",
+            resval: 0x0000_0000
+          }
+        ]
+      }
+    },
+  ],
+}