Make Carfield domains configurable on-demand #245

yvantor · 2023-12-30T16:15:06Z

Make Carfield domains configurable on-demand: domains can be enabled through a dedicated configuration package under hw/configs

yvantor · 2024-01-21T16:50:53Z

This is not complete yet, but is ready to start reviewing it.
The principle is that of allowing multiple configuration packages for enabling/disabling certain islands and defining their memory map. It is based on how it is done in CVA6 to allow different core configurations.

What is missing:

the top-level parametrization is done only for resizing the AXI xbar. This should be done for the RegBus as well.
allow for usage of multiple clusters of the same spieces (e.g. 2 PULP clusters).

Issues encountered:

The code for the Spatz Cluster is still completely Python-generated... This means that if we disable one of the available islands, Questasim will complain at compile time because the AXI ID widths of the Cheshire configuration will no longer match with the ones defined in the Spatz Cluster configuration script. In my honest opinion, we could directly use parametric wrappers instead of Python scripts for System Verilog code generation...
The PULP cluster has a dedicated AXI ports due to the need for AXI ID serializers. This is blocking for the top-level parametrization, so I am considering unifying the ID width in the Cheshire configuration parameter to match the PULP cluster one and remove the need for dedicated master/slave ports.
It is not clear to me why the Mailbox also has dedicated AXI ports. I hope it is not for the same reasons as the point above.

@alex96295 If you have some opinions regarding the code organizations and the perplexities I left above (or if you have more), please let me know.
Of course, opinions from others (@anga93, @micprog, @bluewww, for instance, also @CyrilKoe) are more than welcome!

alex96295 · 2024-01-23T11:31:33Z

@yvantor thanks for the work! I will have a look in the next days and come back at you :)

tb/carfield_fix.sv

hw/carfield_cfg_pkg.sv

Bender.yml

yvantor · 2024-02-07T08:19:00Z

@alex96295 thank you for the review, I will address the comments!

yvantor · 2024-02-07T17:39:12Z

@alex96295 thank you for the review, I will address the comments!

@alex96295 I should have addressed all the points. There is also a PR open in the nonfree for CI updates.

carfield.mk

hw/carfield_cfg_pkg.sv

target/sim/sim.mk

hw/cheshire_wrap.sv

… errors in interrupt assignment for Spatz.

…r and slave devices and use slave IDs structure to compute the memory map.

…enabled.

Using /tmp to store temporary files may cause reusing scripts generated by previous runs

… in CDC generation.

xilinx: Change makefile for new carfield config parameter xilinx: Use islands tcl constraints script xilinx: Mutualize constraints between bd and vanilla xilinx: Remove now unecessary overrides script Appropriate constraints on tc_clk_mux makes overriding them unecessary ci: Remove temporary bender fix, and auto select fpga boards in CI xilinx: Grab rtc_clk in constraints via its net

yvantor · 2024-03-01T19:27:43Z

@alex96295 as soon as the CI completes we can squash and merge.

yvantor · 2024-03-01T20:43:04Z

Forgot to update the non-free rebasing it...

Fix FPGA implementation flow.

yvantor · 2024-03-02T14:14:05Z

Forgot to update the non-free rebasing it...

Solved, it is good to go.

alex96295 · 2024-03-02T14:19:01Z

LGTM, merging

yvantor requested a review from alex96295 as a code owner December 30, 2023 16:15

yvantor self-assigned this Jan 2, 2024

yvantor added the enhancement New feature or request label Jan 2, 2024

yvantor force-pushed the yt/cfg_top branch from 17e30d8 to 8b9da7b Compare January 21, 2024 16:36

yvantor changed the title ~~Draft: create parametric top.~~ Create parametric top. Jan 21, 2024

micprog self-requested a review January 23, 2024 15:12

bluewww self-requested a review February 1, 2024 22:02

yvantor force-pushed the yt/cfg_top branch 4 times, most recently from 0d1e044 to e332604 Compare February 6, 2024 00:05