Make Carfield domains configurable on-demand (#245)

* Create parametric top. Succesfullt excluded Spatz.

* Unified enablers and address ranges in configuration structure. Fixed errors in interrupt assignment
for Spatz.

* Fix peripherals base address.

* Fix lint.

* Fix domain indices generator.

* Create config files for different design targets.

* Fix error in L2 memory map.

* Allow disabling of multiple islands.

* Properly connect CLK and resets to PULP.

* Bump non-free to extend elab-xilinx-base timeout.

* Attempt to fix error in elab-xilinx-base.

* Use correct type for slave indices.

* Propagate configurations to testbench and fistures.

* Use defines to enable bits in FPGA configuration package.

* Fix copy/paste legacy typo.

* Add Spatz wrap to avoid verilog generation.

* Parametrize safety island bootmode selection depending on enabler.

* Contemplate the secure boot option only if security island exists.

* Kill CAN connections if it is not enabled.

* Add configuration files and related targets.

* Drive safety island bootmode in TB avoiding VIP task.

* Clip function for number of AXI master generation.

* Enable security island in full config.

* Align domain indices using the CarfieldDomainIdx parameter.

* Fix isolate signals connections.

* Rename spatz wrap to match synthesys.

* Fix verilog lint.

* 🎨

* Clip IDs computing functions to with maximum number of external master and slave devices
and use slave IDs structure to compute the memory map.

* Specify that config functions and relative parameters are for AXI.

* Cleanup to inforce coherence.

* Fix wrong parameters for L2 memory.

* Bump non-free commit for rebase.

* Bump non-free.

* Use `CarfieldIslandCfg` enabler in passthrough fixture function.

* Proper reordering Bender author's list.

* Reintroduce j variable to track the number of masters and slaves not enabled.

* Unify `carfield_pkg` and `carfield_cfg_pkg`.

* Removing legacy island config from XILINX IP.

* Add comfigurable RegBus address map and move APB mapping scope.

* Renaming for improved clarity.

* Update non-free.

* xilinx: Solving overrides.sh issue
Using /tmp to store temporary files may cause reusing scripts generated by previous runs

* Use localparams to determine the number of AXI devices to be excluded in CDC generation.

* Use top-level parameters for number of AXI CDCs and isolate.

* xilinx: Adapt FPGA constraints to parametrizable top level

xilinx: Change makefile for new carfield config parameter

xilinx: Use islands tcl constraints script

xilinx: Mutualize constraints between bd and vanilla

xilinx: Remove now unecessary overrides script

Appropriate constraints on tc_clk_mux makes overriding them unecessary

ci: Remove temporary bender fix, and auto select fpga boards in CI

xilinx: Grab rtc_clk in constraints via its net

* Update non-free.

* vanilla: Simple fix

---------

Co-authored-by: Yvan Tortorella <[email protected]>
Co-authored-by: Cyril Koenig <[email protected]>

.github/workflows/lint.yml

@@ -42,6 +42,7 @@ jobs:
       uses: chipsalliance/verible-linter-action@main
       with:
         paths: hw
+        exclude_paths: hw/configs
         extra_args: "--waiver_files .github/verible.waiver"
         github_token: ${{ secrets.GITHUB_TOKEN }}
         fail_on_error: true

Bender.yml

@@ -8,6 +8,7 @@ package:
     - "Luca Valente <[email protected]>"
     - "Alessandro Ottaviano <[email protected]>"
     - "Robert Balas <[email protected]>"
+    - "Yvan Tortorella <[email protected]>"
 
 dependencies:
   register_interface: { git: https://github.com/pulp-platform/register_interface.git,   version: 0.4.2                                }
@@ -37,6 +38,39 @@ workspace:
     pulp_cluster: pulp_cluster
 
 sources:
+  # Configurations
+  - target: carfield_l2dual_safe_secure_pulp_spatz_periph_can
+    files:
+      - hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv
+
+  - target: carfield_l2dual_periph
+    files:
+      - hw/configs/carfield_l2dual_periph.sv
+
+  - target: carfield_l2dual_safe_pulp_periph
+    files:
+      - hw/configs/carfield_l2dual_safe_pulp_periph.sv
+
+  - target: carfield_l2dual_pulp_periph
+    files:
+      - hw/configs/carfield_l2dual_pulp_periph.sv
+
+  - target: carfield_l2dual_safe_periph
+    files:
+      - hw/configs/carfield_l2dual_safe_periph.sv
+
+  - target: carfield_l2dual_spatz_periph
+    files:
+      - hw/configs/carfield_l2dual_spatz_periph.sv
+
+  - target: carfield_l2dual_secure_periph
+    files:
+      - hw/configs/carfield_l2dual_secure_periph.sv
+
+  - target: carfield_l2dual_safe_pulp_spatz_periph
+    files:
+      - hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv
+
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
   # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
   # levels 1 and 0, etc. Files within a level are ordered alphabetically.
@@ -48,6 +82,7 @@ sources:
   - hw/cheshire_wrap.sv
   - hw/hyperbus_wrap.sv
   - hw/l2_wrap.sv
+  - hw/spatz_cluster_wrapper.sv
   - hw/carfield_rstgen.sv
   # Level 2
   - hw/carfield.sv
@@ -70,16 +105,16 @@ sources:
   - target: all(xilinx, fpga, xilinx_vanilla)
     files:
       - target/xilinx/src/cdc_dst_axi_err.sv
-      - target/xilinx/src/overrides/tc_clk_xilinx.sv
       - target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
       - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv
+      - target/xilinx/src/overrides/tc_clk_xilinx.sv
 
   - target: all(xilinx, fpga, xilinx_bd)
     files:
       - target/xilinx/src/cdc_dst_axi_err.sv
-      - target/xilinx/src/overrides/tc_clk_xilinx.sv
       - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv
       - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v
+      - target/xilinx/src/overrides/tc_clk_xilinx.sv
 
   - target: intel16_elab_only
     files:

bender-common.mk

@@ -5,6 +5,9 @@
 # Author: Yvan Tortorella <[email protected]>
 # Author: Matteo Perotti <[email protected]>
 
+# Runtime-selectable Carfield configuration
+CARFIELD_CONFIG ?= carfield_l2dual_safe_secure_pulp_spatz_periph_can
+
 # bender targets
 common_targs += -t cva6
 common_targs += -t mchan
@@ -14,6 +17,8 @@ common_targs += -t cv32e40p_use_ff_regfile
 common_targs += -t scm_use_fpga_scm
 common_targs += -t cv64a6_imafdcsclic_sv39
 common_targs += -t rtl
+# Carfield config target.
+common_targs += -t $(CARFIELD_CONFIG)
 
 # bender defines
 common_defs += -D FEATURE_ICACHE_STAT

bender-xilinx.mk

@@ -17,10 +17,6 @@ xilinx_defs_common += -D$(1)=1
 endif
 endef
 
-$(eval $(call check_enable_island,GEN_PULP_CLUSTER))
-$(eval $(call check_enable_island,GEN_SAFETY_ISLAND))
-$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER))
-$(eval $(call check_enable_island,GEN_OPEN_TITAN))
 $(eval $(call check_enable_island,GEN_NO_HYPERBUS))
 $(eval $(call check_enable_island,GEN_EXT_JTAG))
 

carfield.mk

@@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= acda49f
+CAR_NONFREE_COMMIT ?= 54ce7e49
 
 ## @section Carfield platform nonfree components
 ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC

docs/tg/xilinx.md

@@ -41,30 +41,29 @@ Generate the bitstream in `target/xilinx/out/` by running:
 
 ```bash
 make car-xil-all XILINX_FLAVOR=vanilla [VIVADO=version]
-[VIVADO_MODE={batch,gui}] [XILINX_BOARD={vcu128}] [NO_HYPERBUS={0,1}]
-[GEN_EXT_JTAG={0,1}] [GEN_PULP_CLUSTER={0,1}] [GEN_SAFETY_ISLAND={0,1}]
-[GEN_SPATZ_CLUSTER={0,1}] [GEN_OPEN_TITAN={0,1}]
+[VIVADO_MODE={batch,gui}] [XILINX_BOARD={vcu128}] [GEN_NO_HYPERBUS={0,1}]
+[GEN_EXT_JTAG={0,1}] [CARFIELD_CONFIG=carfield_l2dual_{safe,spatz}_periph]
 ```
 
 See the argument list below:
 
-| Argument       | Relevance | Description                                                                                                                           |
-|----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------|
-| VIVADO         | all       | Vivado command to use                                                                                                                 |
-| XILINX_BOARD   | all       | `vcu128`                                                                                                                              |
-| NO_HYPERBUS    | all       | `0` Use the hyperram controller inside `carfield.sv`<br>`1` Use the Xilinx DDR controller                                             |
-| GEN_EXT_JTAG   | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
-| GEN_*[IP]*     | all       | `0` Replace the IP with an AXI error slave<br>`1` Instanciate the IP                                                                  |
-| VIVADO_MODE    | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
+| Argument        | Relevance | Description                                                                                                                           |
+|-----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------|
+| VIVADO          | all       | Vivado command to use                                                                                                                 |
+| XILINX_BOARD    | all       | `vcu128`                                                                                                                              |
+| GEN_NO_HYPERBUS | all       | `0` Use the hyperram controller inside `carfield.sv`<br>`1` Use the Xilinx DDR controller                                             |
+| GEN_EXT_JTAG    | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
+| CARFIELD_CONFIG | all       | Select the Carfield configuration to implement. See below for supported configs.                                                      |
+| VIVADO_MODE     | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
 
 See below some typical building time for reference:
 
-| IPs               | Board  | Duration   |
-|-------------------|--------|------------|
-| PULP              | vcu128 | xxhxxmin   |
-| SAFETY            | vcu128 | xxhxxmin   |
-| SPATZ             | vcu128 | xxhxxmin   |
-| PULP + SAFETY     | vcu128 | xxhxxmin   |
+| Config                                 | Board  | Duration   |
+|----------------------------------------|--------|------------|
+| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
+| carfield_l2dual_safe_periph            | vcu128 | 6h01min    |
+| carfield_l2dual_spatz_periph           | vcu128 | 3h31min    |
+| carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
 xilinx_vanilla)`). This file is used by bender to generate
@@ -91,30 +90,29 @@ Generate the bitstream in `target/xilinx/out/` by running:
 
 ```bash
 make car-xil-all XILINX_FLAVOR=bd [VIVADO=version] [VIVADO_MODE={batch,gui}]
-[XILINX_BOARD={vcu128}] [NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}]
-[GEN_PULP_CLUSTER={0,1}] [GEN_SAFETY_ISLAND={0,1}] [GEN_SPATZ_CLUSTER={0,1}]
-[GEN_OPEN_TITAN={0,1}]
+[XILINX_BOARD={vcu128}] [GEN_NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}]
+[CARFIELD_CONFIG=carfield_l2dual_{safe,spatz}_periph]
 ```
 
 See the argument list below:
 
-| Argument       | Relevance | Description                                                                                                                           |
-|----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------|
-| VIVADO         | all       | Vivado command to use                                                                                                                 |
-| XILINX_BOARD   | all       | `vcu128`                                                                                                                              |
-| NO_HYPERBUS    | all       | `0` Use the hyperram controller inside `carfield.sv`<br>`1` Use the Xilinx DDR controller                                             |
-| GEN_EXT_JTAG   | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
-| GEN_*[IP]*     | all       | `0` Replace the IP with an AXI error slave<br>`1` Instanciate the IP                                                                  |
-| VIVADO_MODE    | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
+| Argument        | Relevance | Description                                                                                                                           |
+|---------------- |-----------|---------------------------------------------------------------------------------------------------------------------------------------|
+| VIVADO          | all       | Vivado command to use                                                                                                                 |
+| XILINX_BOARD    | all       | `vcu128`                                                                                                                              |
+| GEN_NO_HYPERBUS | all       | `0` Use the hyperram controller inside `carfield.sv`<br>`1` Use the Xilinx DDR controller                                             |
+| GEN_EXT_JTAG    | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
+| CARFIELD_CONFIG | all       | Select the Carfield configuration to implement. See below for supported configs.                                                      |
+| VIVADO_MODE     | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
 
 See below some typical building time for reference:
 
-| IPs               | Board  | Duration   |
-|-------------------|--------|------------|
-| PULP              | vcu128 | xxhxxmin   |
-| SAFETY            | vcu128 | xxhxxmin   |
-| SPATZ             | vcu128 | xxhxxmin   |
-| PULP + SAFETY     | vcu128 | xxhxxmin   |
+| Config                                 | Board  | Duration   |
+|----------------------------------------|--------|------------|
+| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
+| carfield_l2dual_safe_periph            | vcu128 | 3h49min    |
+| carfield_l2dual_spatz_periph           | vcu128 | 5h40min    |
+| carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
 xilinx_bd)`). This file is used by bender to generate