feat(perf): Simplify poseidon2 cache zero-pad

[vezenovm]

Description

Problem*

Resolves

Works towards general Brillig bytecode size reductions

Summary*

When actually setting up the state for a poseidon2 permutation, we have a loop to zero-pad the cache and then another loop to add the cache to the state. If we just have a single loop that only adds to the state when the rate index is below the cache size we achieve the same goal with less code.

Additional Context

Documentation*

Check one:

• No documentation needed.
• Documentation included in this PR.
• [For Experimental Features] Documentation to be submitted in a separate PR.

PR Checklist*

• I have tested the changes locally.
• I have formatted the changes with Prettier and/or cargo fmt on default settings.

[github-actions]

Changes to Brillig bytecode sizes

Generated at commit: f7720eb66fdfacfd07f03ae9b29834a6506740ef, compared to commit: 5c4f19f097dd3704522996330c961bf0a2db8d99

🧾 Summary (10% most significant diffs)

Program	Brillig opcodes (+/-)	%
no_predicates_numeric_generic_poseidon	-196 ✅	-12.70%
fold_numeric_generic_poseidon	-196 ✅	-12.70%
poseidon2	-98 ✅	-18.15%

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Full diff report 👇

Program	Brillig opcodes (+/-)	%
eddsa	67,616 (-98)	-0.14%
regression_5252	36,397 (-98)	-0.27%
uhashmap	28,619 (-2,058)	-6.71%
hashmap	49,182 (-4,802)	-8.90%
no_predicates_numeric_generic_poseidon	1,347 (-196)	-12.70%
fold_numeric_generic_poseidon	1,347 (-196)	-12.70%
poseidon2	442 (-98)	-18.15%

[github-actions]

Changes to circuit sizes

Generated at commit: f7720eb66fdfacfd07f03ae9b29834a6506740ef, compared to commit: 5c4f19f097dd3704522996330c961bf0a2db8d99

🧾 Summary (10% most significant diffs)

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
hashmap	+16 ❌	+0.02%	+16 ❌	+0.01%

---

Full diff report 👇

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
hashmap	97,751 (+16)	+0.02%	156,894 (+16)	+0.01%