-
Notifications
You must be signed in to change notification settings - Fork 182
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add cocotb tests for AXI peripherals #1616
base: main
Are you sure you want to change the base?
Conversation
2e334f0
to
f3d5e7c
Compare
CC @proppy - please take a look at this PR |
Does this replace #1057? |
Regarding the content, this PR uses the ideas from #1057 but provides more helpers for writing the simulations. |
I think it'll be easier to maintain it along side the zstd modules for now, and we can generalize it to the wider xls project as it matures. |
19bc572
to
9e77432
Compare
rebase? |
462a6c6
to
a0caa6d
Compare
Rebased onto newest main CC @proppy |
CC @proppy The last CI failure was caused by |
- XLSStruct for easier handling and serializing/deserializing XLS structs - XLSChannel that serves as a dummy receiving channel - XLSMonitor that monitors transactions on an XLS channel - XLSDriver that can send data on an XLS channel - LatencyScoreboard that can measure latency between corresponding transactions on input and output buses - File-backed AXI memory python model Internal-tag: [#64075] Signed-off-by: Krzysztof Obłonczek <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Co-authred-by: Pawel Czarnecki <[email protected]> Co-authred-by: Robert Winkler <[email protected]> Signed-off-by: Michal Czyz <[email protected]> Signed-off-by: Pawel Czarnecki <[email protected]> Signed-off-by: Robert Winkler <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
This PR extends #1613 by adding Verilog simulation and tests for
MemReader
,AxiWriter
andMemWriter
procs. The simulation and testing is carried out with cocotb framework and Icarus Verilog simulator. The PR also includes utilities for driving and monitoring DSLX channels by the cocotb framework.Cocotb and the provided utilities are Python packages and don't require any special rules in the workspace. The utilities we created are generic, and although they were placed in the
xls/modules/zstd/cocotb
directory, they can be moved to another location if this is more desired.Please note that this code is based on top of #1613 so the diff also contains all the changes from that PR. The IR generation for the
MemWriter
proc is also blocked by #1615.