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modules/zstd/BUILD: increase pipeline_stages for DecoderMux proc
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Signed-off-by: Pawel Czarnecki <[email protected]>
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lpawelcz committed Nov 22, 2024
1 parent 26d3208 commit f2e9dab
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions xls/modules/zstd/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -506,7 +506,7 @@ xls_dslx_verilog(
codegen_args = {
"module_name": "DecoderMux",
"delay_model": "asap7",
"pipeline_stages": "2",
"pipeline_stages": "3",
"reset": "rst",
"use_system_verilog": "false",
},
Expand All @@ -520,7 +520,7 @@ xls_benchmark_ir(
name = "dec_mux_opt_ir_benchmark",
src = ":dec_mux_verilog.opt.ir",
benchmark_ir_args = {
"pipeline_stages": "2",
"pipeline_stages": "10",
"delay_model": "asap7",
},
tags = ["manual"],
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