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Value from const array used in loop range fails assertion in the typechecker
#1664
opened Oct 17, 2024 by
koblonczek
Consolidate apfloat "round with ties to nearest even" logic
cleanup
Tech debt reduction, factoring, consolidation, rework, etc.
dslx
DSLX (domain specific language) implementation / front-end
#1656
opened Oct 9, 2024 by
mikex-oss
[enhancement] Add runtime-constant values & channels
enhancement
New feature or request
#1653
opened Oct 8, 2024 by
ericastor
[enhancement] Block Conversion for New-Style Procs
codegen
Related to emitting (System)Verilog.
enhancement
New feature or request
🧦 sox
stitching
Issues related to stitching, multi-proc codegen, and integration with external verilog modules
#1652
opened Oct 7, 2024 by
grebe
[enhancement] AOT support for block-IR JIT
enhancement
New feature or request
jit
🧦 sox
#1651
opened Oct 7, 2024 by
grebe
[enhancement] Rethink Channel Legalization
codegen
Related to emitting (System)Verilog.
enhancement
New feature or request
#1647
opened Oct 4, 2024 by
grebe
[enhancement] DSLX Polymorphism
dslx
DSLX (domain specific language) implementation / front-end
enhancement
New feature or request
#1646
opened Oct 4, 2024 by
grebe
Simplify: use one form of serialization used by fuzzer and ir/verilog simulation
#1645
opened Oct 3, 2024 by
hzeller
Use same flag names for equivalent inputs in
eval_proc_main
and simulate_module_main
#1644
opened Oct 3, 2024 by
hzeller
[enhancement] Put module_builder's functions in a shared package
codegen
Related to emitting (System)Verilog.
enhancement
New feature or request
#1643
opened Oct 3, 2024 by
grebe
[enhancement] Name legalization should choose keywords based on configuration
codegen
Related to emitting (System)Verilog.
enhancement
New feature or request
#1641
opened Oct 2, 2024 by
grebe
[enhancement] Add support for node-EvaluationObservers on AOTd code
enhancement
New feature or request
#1639
opened Sep 27, 2024 by
allight
[enhancement] Make an easy path to add DSLX models to a DUT
enhancement
New feature or request
#1638
opened Sep 27, 2024 by
grebe
Extern types don't codegen correctly when array-typed
codegen
Related to emitting (System)Verilog.
#1637
opened Sep 27, 2024 by
grebe
[fuzzer 2024-09-26_ac56] Different results between IR and IR-opt
fuzz
jit
#1636
opened Sep 27, 2024 by
hzeller
ir_conv: chan array cannot be created from from existing chans
dslx
DSLX (domain specific language) implementation / front-end
ir
🧦 sox
#1631
opened Sep 25, 2024 by
proppy
Refactor channel->port mapping in signature
codegen
Related to emitting (System)Verilog.
stitching
Issues related to stitching, multi-proc codegen, and integration with external verilog modules
#1628
opened Sep 24, 2024 by
grebe
[enhancement] XLS playground colab should be documented in our markdown docs
documentation
Improvements or additions to documentation
enhancement
New feature or request
#1626
opened Sep 24, 2024 by
cdleary
Document Improvements or additions to documentation
ir
array_concat
IR operation
documentation
#1619
opened Sep 20, 2024 by
ericastor
jit crash, 2024-09-20_67c5
bug
Something isn't working or is incorrect
fuzz
jit
#1618
opened Sep 20, 2024 by
hzeller
Hoist operations above selects if it enables constant folding
optimizer
Related to IR optimization or analysis
#1611
opened Sep 18, 2024 by
meheff
cpp_transpiler should emit DSLX constants
enhancement
New feature or request
🧦 sox
#1610
opened Sep 17, 2024 by
mikex-oss
cpp_transpiler should emit an array of all DSLX enum members
enhancement
New feature or request
🧦 sox
#1603
opened Sep 12, 2024 by
mikex-oss
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What’s not been updated in a month: updated:<2024-09-17.