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Added parallelism to euvm port#917

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puneet wants to merge 87 commits intochipsalliance:masterchipsalliance/riscv-dv:masterfrom coverify:mastercoverify/riscv-dv:masterCopy head branch name to clipboard

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Commits

Commits on Nov 24, 2022

• Fixed some syntactic style inconsistencies

  puneet

  committed
  38b35f6

• Fixed s core setting parameter as enum

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  3e06f91

• Added makefile target for pmp test

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  41b7e80

• Uncommented a "solve before" constraint that was inadvertantly commneted

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  0ccd6f0

• Fixed an issue with pmp configuration

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  85fecec

• Misc fixes

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  008921f

• Fizes for 32 bit RISCV

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  45072b9

• Added and used append and prepend functions for instr_list

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  5eb63d8

• Create and use new class riscv_prog_instr_stream

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  e432b45

• Refactored mixing of directed instructions in the prog instr_list

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  83ab325

• Use forked parallism while generating big chuck of instrutions

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  da1b945

• Generate directed stream on multiple cores

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  d782a64

• Add parallelization parameters to config and use these

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  9161dc9

• Fixed compilation issues

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  0f087ac

• fixes in makefile

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  21f000d

• Fix imm_str for performance

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  59a7425

• Tag overriding constraint with constraint_override

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  6cd7f5e

• Add command line options for par_num_threads and par_instr_threshold

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  9bb0f9f

• Fixed instruction randomization for performance

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  3c76ed3

• Disable GC when the instruction dump is generated

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  9010aca

• Add constraint_override tag for overriding constraint

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  f04f41d

• Pass command line config for par_num_threads to riscv-dv config

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  aaa4680

• Add compile optiond for LTO

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  ed12769

• Rearrange instr sequence to avoid push_front

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  puneet

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  6faee00

• Fix atomicity os subprogram calls

  puneet

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  8c09cf9

• Fix riscv_instr_test

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  e7a7baf

• Use format in place of format_string

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  8d52ad0

• Renamed string enum indent as INDENT

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  9da703a

Commits on Nov 25, 2022

• Use ScratchPad to enable faster convert2asm functionality

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  committed
  957107a

Commits on Nov 30, 2022

• Fix directed stream naming

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  committed
  e4e14f7

Commits on Jan 16, 2023

• [eUVM] Added rv64imafdc target

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  committed
  3edfd4a

• [eUVM][epmp] Add support for mseccfg CSR

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  a5becd4

• [eUVM] fix chipsalliance#819

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  5303612

• [eUVM][Smepmp] Fixes gen_pmp_instr when MML and MMWP are enabled

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  c6bac4f

• [eUVM] Allow for WFI in User Mode

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  75be07a

Commits on Jul 25, 2023

• Refactored a randomize with constraint for riscv-instr

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  81eb25b

Commits on Sep 26, 2023

• Merge branch 'chipsalliance:master' into master

  puneet

  authored
  7b7a4ed

Commits on Nov 18, 2023

• Extend CI matrix

  

  eszpotanski

  authored and

  puneet

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  4c10620

• Fixes to support RV32

  Show description for 244e40a
  

  mkurc-ant

  authored and

  puneet

  committed
  244e40a

Commits on Jan 9, 2024

• [euvm] Refactor CSR instruction into their own class

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  eeb3e31

• [euvm] Expand CSR instruction constraint functionality

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  f54f8b8

• [euvm] [pmp] No PMP exception handler when no PMP support

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  c9ce158

• [euvm] Tweak CSR constraints for more even read/write distribution

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  da3f31f

• [euvm] [pmp] Randomizing entry for instructions for PMP randomization

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  30e91ca

• [euvm] [pmp] Allow specifying address zero in +pmp_region_%0d

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  42fd051

• [euvm] [pmp] Use random address instead of offset for full random test

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  a38f4fc

• [euvm] [pmp] Fix constraint and CSR write test in MML mode

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  c5b70a5

• [euvm] [pmp] Add already_configured flag to skip address in PMP routine

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  652f83a

• [euvm] [pmp] Add PMP entries for data in case of MML or MMWP

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  8ae0b92

• [euvm] [pmp] Remove restriction on using NAPOT when granularity = 0

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  a6f7f88

• [euvm] [pmp] Add knob to suppress PMP setup code

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  65558f5

• [euvm] Add plusarg to enable ECALL insn in main randomized body

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  dbc73da

• [euvm] [sv] Explicit type casting for VCS compability

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  767a804

• [euvm] [pmp] Put signature and stack in last PMP entries

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  b5d45b8

• [euvm] [pmp] Add end of kernel stack to stack entry

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  e4a5770

• [euvm] [pmp] Use kernel_inst_end for end of code entry

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  6d61854

• [euvm] [pmp] Allow already configured addresses to be overwritten with plusargs

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  81dea5b

• [euvm] [pmp] Check for MML before modifying PMP entry in trap handler

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  2ee4baf

• [euvm] [pmp] Store and load faults caused by locked PMP regions now skip to next instruction

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  0d33f94

• [euvm] [pmp] Try to skip instruction if no PMP match and in MMWP

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  59d48d5

• [euvm] [pmp] Add illegal TOR and NAPOT address mode constraints

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  7dce3ea

• [euvm] [pmp] Add a register for loop counter in PMP traps instead of mscratch

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  5061582

• [euvm] [pmp] Improve formatting of PMP addresses for debug

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  ac7f02f

• [euvm] [pmp] Fix plusarg detection for MML and MMWP

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  7c00fda

• [euvm] Store user-stack-pointer on kernel stack when pushing/popping GPRs

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  8377f24

• [euvm] Reserve one extra word when pushing GPRs to kernel stack

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  a11bb49

• [euvm] Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions

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  f0a4179

• [euvm] Issue chipsalliance#778 fix, change mie behavior in setup_mmode_reg

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  8d3f233

• [euvm] randomizing mstatus.MIE when priv mode is lower than machine

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  8d1f8ca

• [euvm] Fix for issue chipsalliance#826, illegal rs1 in C_JALR

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  a01579a

• [euvm] [pmp] Add option to constrain addresses to stay in 32-bit space

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  b40c187

• [euvm] [pmp] Ensure MML PMP configurations don't dominate.

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  998c0c4

• [euvm] [Page Table]Fix issue#926 issue#846, NEXT_LEVEL_PAGE entry's a,d,u should be 0

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  feb9a73

• [euvm] [pmp] Remove MSECCFG reads from trap handler when Smepmp is disabled

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  07ef0d0

• [euvm] Prefer using UBVEC than toubvec for constant bvec values

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  21d87d1

• All vector instructions are now registered individually

  Show description for bf6b484
  puneet

  committed
  bf6b484

Commits on Feb 27, 2024

• Fixes to support RV32

  Show description for 170b5db
  

  mkurc-ant

  authored and

  puneet

  committed
  170b5db

• First step towards converging with riscv-opcodes project

  puneet

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  334fba5

• Use tallocator for fast multicode memory allocations

  puneet

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  2ae196d

• Added partial support for riscv opcodes package

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  6fe39f9

• Fixes for 32 bit RISCV

  puneet

  committed
  f170d0c

• Fixes to support RV32

  Show description for ef040f4
  

  mkurc-ant

  authored and

  puneet

  committed
  ef040f4

• Fixes for 32 bit RISCV

  puneet

  committed
  ce01c2f

• Added p-extension instructions to gen/isa

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  29ce0e9

• Added rv64imp as target

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  e44b7a3

• Converged with the riscv-opcode project

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  a7a56c7

• Fixed some compilation issues

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  committed
  4a68deb