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Pull requests: chipsalliance/riscv-dv

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Pull requests list

Fix mismatch in push stack logic for branch instruction generation
#995 opened Dec 11, 2024 by Bounti Loading…
1
Make renode_wrapper more configurable
#991 opened Aug 28, 2024 by MateuszKarlic Loading…
added options and information for siemens questasim simulator support…
#989 opened Jul 18, 2024 by ludovicpion Loading…
1
run: fix disabling the c extension
#988 opened Jul 12, 2024 by fkokosinski Loading…
Fix CSR test generation for RV64
#987 opened Jul 9, 2024 by serge0699 Loading…
updated for python 3.12
#985 opened Jul 9, 2024 by 5hayanB Loading…
allow specifying privilege modes for simulation
#984 opened Jun 28, 2024 by wsipak Loading…
Fix gen_callback
#983 opened Jun 20, 2024 by HuashuQ Loading…
4
Fix isa and mabi argument handling
#980 opened May 28, 2024 by koblonczek Loading…
1
Fix XLEN assumption in riscv_instr_pkg
#925 opened Feb 17, 2023 by dpetrisko Loading…
3
Add new extensions Zcb, Zfh, Zbkb, partial Zfa
#921 opened Jan 30, 2023 by JJ-Gaisler Loading…
9
There is a bug in the instruction function coverage. The store rs1 an…
#920 opened Jan 4, 2023 by Aaron-LI-777 Loading…
1
Added parallelism to euvm port
#917 opened Nov 30, 2022 by puneet Loading…
Update metrics-regress.yml
#909 opened Nov 9, 2022 by pradheepkaliraj • Draft
5
for issue 807 modify the logic
#894 opened Aug 24, 2022 by mukesh891 Loading…
1
[PyFlow] Update B extension source files for PyFlow
#855 opened Mar 30, 2022 by aneels3 Loading…
1
[PyFlow] Add support for privilege modes
#854 opened Mar 3, 2022 by aneels3 Loading…
5
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