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Interlagos
Thomas.Roehl edited this page Nov 5, 2015
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AMD Interlagos Performance groups
The input file for the events on AMD K8 can be found here.
The AMD® Interlagos microarchitecture provides 6 general-purpose counters consiting of a config and a counter register.
Counter name | Event name |
---|---|
PMC0 | * |
PMC1 | * |
PMC2 | * |
PMC3 | * |
PMC4 | * |
PMC5 | * |
Option | Argument | Description | Comment |
---|---|---|---|
edgedetect | N | Set bit 18 in config register | |
kernel | N | Set bit 17 in config register | |
threshold | 8 bit hex value | Set bits 24-31 in config register | The value for threshold can range between 0x0 and 0x1F |
invert | N | Set bit 23 in config register |
The AMD® Interlagos microarchitecture provides 4 general-purpose counters for the Northbridge consisting of a config and a counter register.
Counter name | Event name |
---|---|
UPMC0 | * |
UPMC1 | * |
UPMC2 | * |
UPMC3 | * |
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