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Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench #107

Merged
merged 9 commits into from
Feb 15, 2021
Merged

Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench #107

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7295555
integrate newer uart
jjts Feb 8, 2021
5481a90
working with new uart hardware, booting being improved, can run canno…
jjts Feb 9, 2021
76e69de
program loading working in simulation, not yet console
jjts Feb 10, 2021
e565ee0
working with new console and uart
jjts Feb 10, 2021
19ce9ed
console abstracts from comm medium: preparing socket comm
jjts Feb 10, 2021
012a424
add comm modules
jjts Feb 10, 2021
84db182
console and boot exchanging files
jjts Feb 11, 2021
3e659e5
Merge branch 'uartdev' into verilator
slahiruk Feb 12, 2021
7f0177e
adding model top level code from FPGA wrapper for full system simulation
slahiruk Feb 15, 2021
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2 changes: 2 additions & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,8 @@ software/firmware/*
software/console/*
!software/console/console.c
!software/console/console.h
!software/console/rs232comm.c
!software/console/socketcomm.c
!software/console/Makefile

document/presentation/*
Expand Down
5 changes: 5 additions & 0 deletions hardware/hardware.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,11 @@ ifeq ($(USE_DDR),1)
include $(CACHE_DIR)/hardware/hardware.mk
endif

#interconect
INTERCON_DIR:=$(CACHE_DIR)/submodules/INTERCON
include $(INTERCON_DIR)/hardware/hardware.mk


#rom
ifneq ($(ASIC),1)
SUBMODULES+=SPROM
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152 changes: 57 additions & 95 deletions hardware/include/cpu_tasks.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
//
// CPU TASKS
//
//
// CPU TASKS TO CONTROL THE TESTBENCH UART
//
//this is a temporary solution

//address macros
`define UART_SOFTRESET_ADDR 0
`define UART_DIV_ADDR 1
`define UART_TXDATA_ADDR 2
`define UART_TXEN_ADDR 3
`define UART_TXREADY_ADDR 4
`define UART_RXDATA_ADDR 5
`define UART_RXEN_ADDR 6
`define UART_RXREADY_ADDR 7


// 1-cycle write
task cpu_uartwrite;
Expand All @@ -9,7 +21,7 @@

# 1 uart_addr = cpu_address;
uart_valid = 1;
uart_wstrb = 1;
uart_wstrb = 4'hf;
uart_wdata = cpu_data;
@ (posedge clk) #1 uart_wstrb = 0;
uart_valid = 0;
Expand All @@ -26,24 +38,53 @@
@ (posedge clk) #1 uart_valid = 0;
endtask //cpu_uartread

task cpu_inituart;
//pulse reset uart
cpu_uartwrite(`UART_SOFTRESET_ADDR, 1);
cpu_uartwrite(`UART_SOFTRESET_ADDR, 0);
//config uart div factor
cpu_uartwrite(`UART_DIV_ADDR, `FREQ/`BAUD);
//enable uart for receiving
cpu_uartwrite(`UART_RXEN_ADDR, 1);
cpu_uartwrite(`UART_TXEN_ADDR, 1);
endtask

reg [7:0] rxread_reg = 8'b0;

task cpu_getchar;
output [7:0] rcv_char;

//wait until something is received
do
cpu_uartread(`UART_RXREADY_ADDR, rxread_reg);
while(!rxread_reg);

//read the data
cpu_uartread(`UART_RXDATA_ADDR, rxread_reg);

rcv_char = rxread_reg[7:0];
endtask


task cpu_putchar;
input [7:0] send_char;
//wait until tx ready
do begin
cpu_uartread(`UART_TXREADY_ADDR, rxread_reg);
end while(!rxread_reg);
//write the data
cpu_uartwrite(`UART_TXDATA_ADDR, send_char);

endtask

task cpu_sendfile;
reg [`DATA_W-1:0] file_size;
reg [7:0] char;
integer fp;
integer res;
integer i, k;

//signal target to expect data
cpu_putchar(`FRX);

//print incoming messages
cpu_print();

//wait for target
do cpu_getchar(cpu_char);
while (cpu_char != `FRX);

//open data file
//open data file
fp = $fopen("firmware.bin","rb");

// Get file size
Expand All @@ -55,9 +96,6 @@
file_size = $ftell(fp);
res = $rewind(fp);

//Signal target ACK
cpu_putchar(`ACK);

$display("File size: %d bytes", file_size);

//Send file size
Expand All @@ -66,7 +104,7 @@
cpu_putchar(file_size[23:16]);
cpu_putchar(file_size[31:24]);

//Send file
//Send file
k = 0;
for(i = 0; i < file_size; i++) begin
cpu_putchar($fgetc(fp));
Expand All @@ -92,8 +130,6 @@

fp = $fopen("out.bin", "wb");

cpu_print();

// Send file size
cpu_getchar(file_size[7:0]);
cpu_getchar(file_size[15:8]);
Expand All @@ -115,80 +151,6 @@

$fclose(fp);

cpu_print();

endtask


task cpu_inituart;
//pulse reset uart
cpu_uartwrite(`UART_SOFT_RESET, 1);
cpu_uartwrite(`UART_SOFT_RESET, 0);
//config uart div factor
cpu_uartwrite(`UART_DIV, `FREQ/`BAUD);
//enable uart for receiving
cpu_uartwrite(`UART_RXEN, 1);
cpu_uartwrite(`UART_TXEN, 1);
endtask

reg [7:0] rxread_reg = 8'b0;

task cpu_getchar;
output [7:0] rcv_char;

//wait until something is received
do
cpu_uartread(`UART_READ_VALID, rxread_reg);
while(!rxread_reg);

//read the data
cpu_uartread(`UART_DATA, rxread_reg);

rcv_char = rxread_reg[7:0];
endtask


task cpu_putchar;
input [7:0] send_char;
//wait until tx ready
do begin
cpu_uartread(`UART_WRITE_WAIT, rxread_reg);
end while(rxread_reg);
//write the data
cpu_uartwrite(`UART_DATA, send_char);

endtask

task cpu_getline;
reg [7:0] char;
do begin
cpu_getchar(char);
$write("%c", char);
end while (char != "\n");
endtask

//connect with targe
task cpu_connect;
do cpu_getchar(cpu_char);
while (cpu_char != `ENQ);
cpu_putchar(`ACK);
endtask

task cpu_run;
//do cpu_getchar(cpu_char);
//while (cpu_char != `ENQ);
cpu_putchar(`EOT);
cpu_print();
endtask

task cpu_print;
do cpu_getchar(cpu_char);
while (cpu_char != `STX);

cpu_getchar(cpu_char);
while(cpu_char != `ETX && cpu_char != `ENQ) begin
$write("%c", cpu_char);
cpu_getchar(cpu_char);
end

endtask
37 changes: 24 additions & 13 deletions hardware/testbench/system_core_tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ module system_tb;
reg uart_valid;
reg [`UART_ADDR_W-1:0] uart_addr;
reg [`DATA_W-1:0] uart_wdata;
reg uart_wstrb;
reg [3:0] uart_wstrb;
reg [`DATA_W-1:0] uart_rdata;
wire uart_ready;

Expand Down Expand Up @@ -57,20 +57,31 @@ module system_tb;

// configure uart
cpu_inituart();

//connect with bootloader
cpu_connect();

`ifdef LD_FW
//send program
cpu_sendfile();
//uncomment for debug
//cpu_receivefile();

while(1) begin
cpu_getchar(cpu_char);

case(cpu_char)
`ENQ: begin
`ifdef LD_FW //send program
cpu_putchar(`FRX);
cpu_getchar(cpu_char); //remove extra ENQ received
cpu_sendfile();
`else
cpu_putchar(`ACK);
`endif
//run firmware
cpu_run();
end

$finish;
`EOT: begin
$finish;
end

default: begin
$write("%c", cpu_char);
end

endcase
end

end

Expand Down
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