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Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench #107

Merged
merged 9 commits into from
Feb 15, 2021

adding model top level code from FPGA wrapper for full system simulation

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Merged

Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench #107

adding model top level code from FPGA wrapper for full system simulation
7f0177e
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