Merge pull request #234 from PedroAntunes178/masterMerge

Master merge

Makefile

@@ -111,8 +111,6 @@ clean:
 	make sim-clean
 	make fpga-clean
 	make doc-clean
-	make console-clean
-#	make asic-clean
 
 clean-all: test-clean
 

document/presentation/presentation.tex

@@ -78,7 +78,7 @@
       \item The IOb-SoC template eases this task by providing a base Verilog SoC equipped with
         \begin{itemize}
         \item a RISC-V CPU
-        \item a memory system including boot ROM, RAM, 2-level cache system and AXI4 interface to external memory (DDR)
+        \item a memory system including boot ROM, RAM, 2-level cache system and an AXI4 interface to external memory (DDR)
         \item a UART communications module
         \item an example firmware program
         \end{itemize}
@@ -91,11 +91,11 @@
 \begin{frame}{Project setup}
 \begin{center}
   \begin{itemize}
-    \item Use a Linux real or virtual machine
-    \item Make sure you a {\bf stable} version of the open source Icarus Verilog simulator (\url{iverilog.icarus.com}) installed locally or into some remote server
+    \item Use a Linux real or virtual machine (see the README file to download a VM)
+    \item Make sure you a {\bf stable} version of the open source Icarus Verilog simulator (\url{iverilog.icarus.com}) is installed locally or on some remote server
     \item Make sure you have FPGA build tools installed locally or on some remote server
     \item Make sure you have an FPGA board attached to your Linux machine or to some remote server
-    \item Set up {\bf ssh} access key to GitHub (\url{github.com}) (https access requires you to enter your password many times)
+    \item Set up {\bf ssh} access key to GitHub (\url{github.com}) (using https will ask for your password many times)
     \item Follow the instructions in the IOb-SoC repository's README file to clone the repository and install the tools
   \end{itemize}
 \end{center}
@@ -107,7 +107,7 @@
   \item The Timer IP core at \url{github.com/IObundle/iob-timer.git} is used here as an example
   \item Add the Timer IP core repository as a git submodule of your IOb-SoC clone repository:\\
     {\tt \tiny git submodule add [email protected]:IObundle/iob-timer.git submodules/TIMER}
-  \item Update the Timer IP core submodules, so one can use the new IP core:\\
+  \item Update the Timer IP core submodules:\\
     {\tt \tiny git submodule update ----init ----recursive}
   \item Add the Timer IP core to the list of peripherals in the {\tt ./system.mk} file:\\
     {\tt PERIPHERALS:=UART {\em TIMER}}
@@ -188,8 +188,7 @@
 \begin{frame}{Run IOb-SoC on an FPGA board (1)}
 \begin{itemize}
 \item To compile and run your SoC in one of our FPGA boards, contacts us at [email protected].
-\item To compile and run your SoC on your FPGA board, add a directory into {\tt ./hardware/fpga},
-  using the existing board directories as examples
+\item To compile and run your SoC on your FPGA board, add a directory into {\tt ./hardware/fpga/<toolchain>}, where <toolchain> is either *vivado* or *quartus*. Use the existing board directories as examples
 \item Then issue the following command:\\
   {\tt make run BOARD=<board\_dir\_name> INIT\_MEM=0}\\
   This will compile the software and the hardware, produce an FPGA bitstream,

hardware/fpga/fpga.mk

@@ -25,13 +25,13 @@ FORCE ?= 0
 run:
 ifeq ($(NORUN),0)
 ifeq ($(BOARD_SERVER),)
-	if [ ! -f $(LOAD_FILE) ]; then touch $(LOAD_FILE); chmod 664 $(LOAD_FILE); chown $(USER):dialout $(LOAD_FILE); fi;\
-	bash -c "trap 'make queue-out' INT; make queue-in; if [ $(FORCE) = 1 -o \"`head -1 $(LOAD_FILE)`\" != \"$(JOB)\" ];\
+	if [ ! -f $(LOAD_FILE) ]; then touch $(LOAD_FILE); chown $(USER):dialout $(LOAD_FILE); chmod 664 $(LOAD_FILE); fi;\
+	bash -c "trap 'make queue-out' INT TERM KILL; make queue-in; if [ $(FORCE) = 1 -o \"`head -1 $(LOAD_FILE)`\" != \"$(JOB)\" ];\
 	then ../prog.sh; echo $(JOB) > $(LOAD_FILE); fi; make -C $(CONSOLE_DIR) run; make queue-out"
 else
 	ssh $(BOARD_USER)@$(BOARD_SERVER) 'if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi'
 	rsync -avz --exclude .git $(ROOT_DIR) $(BOARD_USER)@$(BOARD_SERVER):$(REMOTE_ROOT_DIR) 
-	bash -c "trap 'make queue-out-remote' INT; ssh $(BOARD_USER)@$(BOARD_SERVER) 'make -C $(REMOTE_ROOT_DIR)/hardware/fpga/$(TOOL)/$(BOARD) $@ INIT_MEM=$(INIT_MEM) FORCE=$(FORCE) TEST_LOG=\"$(TEST_LOG)\"'"
+	bash -c "trap 'make queue-out-remote' INT TERM KILL; ssh $(BOARD_USER)@$(BOARD_SERVER) 'make -C $(REMOTE_ROOT_DIR)/hardware/fpga/$(TOOL)/$(BOARD) $@ INIT_MEM=$(INIT_MEM) FORCE=$(FORCE) TEST_LOG=\"$(TEST_LOG)\"'"
 ifneq ($(TEST_LOG),)
 	scp $(BOARD_USER)@$(BOARD_SERVER):$(REMOTE_ROOT_DIR)/software/console/test.log $(CONSOLE_DIR)
 endif
@@ -64,9 +64,9 @@ endif
 # Board access queue
 #
 queue-in:
-	if [ ! -f $(QUEUE_FILE) ]; then touch $(QUEUE_FILE); chmod 644 $(QUEUE_FILE); chown $(USER):dialout $(QUEUE_FILE); fi;\
+	if [ ! -f $(QUEUE_FILE) ]; then touch $(QUEUE_FILE); chown $(USER):dialout $(QUEUE_FILE); chmod 664 $(QUEUE_FILE); fi;\
 	if [ "`head -1 $(QUEUE_FILE)`" != "$(JOB)" ]; then echo $(JOB) >> $(QUEUE_FILE); fi;\
-	bash -c "trap 'make queue-out; exit' INT; make queue-wait"
+	bash -c "trap 'make queue-out; exit' INT TERM KILL; make queue-wait"
 
 queue-wait:
 	while [ "`head -1 $(QUEUE_FILE)`" != "$(JOB)" ]; do echo "Job queued for board access. Queue length: `wc -l $(QUEUE_FILE) | cut -d" " -f1`"; sleep 10s; done
@@ -84,15 +84,18 @@ queue-out-remote:
 #
 
 test: clean-testlog test1 test2 test3
-	diff -q $(CONSOLE_DIR)/test.log test.expected
+	mv $(CONSOLE_DIR)/test.log .
+	diff -q test.log test.expected
 
-test1: clean
+test1:
+	make clean
 	make all INIT_MEM=1 USE_DDR=0 RUN_EXTMEM=0 TEST_LOG=">> test.log";\
 
 test2: 
 	make all INIT_MEM=0 USE_DDR=0 RUN_EXTMEM=0 TEST_LOG=">> test.log";\
 
-test3: clean
+test3:
+	make clean
 	make all INIT_MEM=0 USE_DDR=1 RUN_EXTMEM=1 TEST_LOG=">> test.log";\
 
 

hardware/fpga/vivado/AES-KU040-DB-G/verilog/top_system.v

@@ -419,7 +419,7 @@ module top_system(
       .m_axi_wready  (sys_wready),
 
       //write response
-      //.m_axi_bid     (sys_bid),
+      .m_axi_bid     (sys_bid),
       .m_axi_bresp   (sys_bresp),
       .m_axi_bvalid  (sys_bvalid),
       .m_axi_bready  (sys_bready),
@@ -438,7 +438,7 @@ module top_system(
       .m_axi_arready (sys_arready),
 
       //read   
-      //.m_axi_rid     (sys_rid),
+      .m_axi_rid     (sys_rid),
       .m_axi_rdata   (sys_rdata),
       .m_axi_rresp   (sys_rresp),
       .m_axi_rlast   (sys_rlast),

hardware/simulation/simulation.mk

@@ -46,7 +46,7 @@ ifeq ($(SIM_SERVER),)
 else
 	ssh $(SIM_USER)@$(SIM_SERVER) "if [ ! -d $(REMOTE_ROOT_DIR) ]; then mkdir -p $(REMOTE_ROOT_DIR); fi"
 	rsync -avz --exclude .git $(ROOT_DIR) $(SIM_USER)@$(SIM_SERVER):$(REMOTE_ROOT_DIR)
-	bash -c "trap 'make kill-remote-sim' INT; ssh $(SIM_USER)@$(SIM_SERVER) 'make -C $(REMOTE_ROOT_DIR)/hardware/simulation/$(SIMULATOR) run INIT_MEM=$(INIT_MEM) USE_DDR=$(USE_DDR) RUN_EXTMEM=$(RUN_EXTMEM) VCD=$(VCD) TEST_LOG=\"$(TEST_LOG)\"'"
+	bash -c "trap 'make kill-remote-sim' INT TERM KILL; ssh $(SIM_USER)@$(SIM_SERVER) 'make -C $(REMOTE_ROOT_DIR)/hardware/simulation/$(SIMULATOR) run INIT_MEM=$(INIT_MEM) USE_DDR=$(USE_DDR) RUN_EXTMEM=$(RUN_EXTMEM) VCD=$(VCD) TEST_LOG=\"$(TEST_LOG)\"'"
 ifneq ($(TEST_LOG),)
 	scp $(SIM_USER)@$(SIM_SERVER):$(REMOTE_ROOT_DIR)/hardware/simulation/$(SIMULATOR)/test.log $(SIM_DIR)
 endif

hardware/simulation/xcelium/Makefile

@@ -4,8 +4,8 @@ defmacro:=-define
 incdir:=-incdir 
 
 SIMULATOR=xcelium
-SIM_SERVER ?=$(XMSIM_SERVER)
-SIM_USER ?=$(XMSIM_USER)
+SIM_SERVER ?=$(CADENCE_SERVER)
+SIM_USER ?=$(CADENCE_USER)
 SIM_PROC=xmsim
 
 include ../simulation.mk

hardware/src/ext_mem.v

@@ -41,6 +41,7 @@ module ext_mem
     output                                   axi_wlast,
     output                                   axi_wvalid, 
     input                                    axi_wready,
+    input [0:0]                              axi_bid,
     input [1:0]                              axi_bresp,
     input                                    axi_bvalid,
     output                                   axi_bready,
@@ -57,6 +58,7 @@ module ext_mem
     output                                   axi_arvalid, 
     input                                    axi_arready,
     //Read
+    input [0:0]                              axi_rid,
     input [`DATA_W-1:0]                      axi_rdata,
     input [1:0]                              axi_rresp,
     input                                    axi_rlast, 

hardware/src/system_core.v

@@ -33,7 +33,7 @@ module system
    input                    m_axi_wready,
 
    //write response
-   //input [0:0]              m_axi_bid,
+   input [0:0]              m_axi_bid,
    input [1:0]              m_axi_bresp,
    input                    m_axi_bvalid,
    output                   m_axi_bready,
@@ -52,7 +52,7 @@ module system
    input                    m_axi_arready,
 
    //read
-   //input [0:0]              m_axi_rid,
+   input [0:0]              m_axi_rid,
    input [`DATA_W-1:0]      m_axi_rdata,
    input [1:0]              m_axi_rresp,
    input                    m_axi_rlast, 
@@ -276,7 +276,7 @@ module system
       .axi_wvalid(m_axi_wvalid), 
       .axi_wready(m_axi_wready), 
       //write response
-      //.axi_bid(m_axi_bid), 
+      .axi_bid(m_axi_bid),
       .axi_bresp(m_axi_bresp), 
       .axi_bvalid(m_axi_bvalid), 
       .axi_bready(m_axi_bready), 
@@ -293,7 +293,7 @@ module system
       .axi_arvalid(m_axi_arvalid), 
       .axi_arready(m_axi_arready), 
       //read 
-      //.axi_rid(m_axi_rid), 
+      .axi_rid(m_axi_rid),
       .axi_rdata(m_axi_rdata), 
       .axi_rresp(m_axi_rresp), 
       .axi_rlast(m_axi_rlast), 

hardware/testbench/system_core_tb.v

@@ -187,7 +187,7 @@ module system_tb;
 	       .m_axi_wready  (ddr_wready),
 
 	       //write response
-	       //.m_axi_bid     (ddr_bid[0]),
+	       .m_axi_bid     (ddr_bid[0]),
 	       .m_axi_bresp   (ddr_bresp),
 	       .m_axi_bvalid  (ddr_bvalid),
 	       .m_axi_bready  (ddr_bready),
@@ -206,7 +206,7 @@ module system_tb;
 	       .m_axi_arready (ddr_arready),
 
 	       //read   
-	       //.m_axi_rid     (ddr_rid[0]),
+	       .m_axi_rid     (ddr_rid[0]),
 	       .m_axi_rdata   (ddr_rdata),
 	       .m_axi_rresp   (ddr_rresp),
 	       .m_axi_rlast   (ddr_rlast),

software/python/get_memsize.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/python2
 
 import sys
 import subprocess

software/python/hex_split.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/python2
 
 import string
 from sys import argv

software/python/makehex.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/python2
 
 from sys import argv
 

software/python/memwrapper_make.py

@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/python2
 
 #ram usage: memwrapper_make tech type words bits bytes mux
 #rom usage: memwrapper_make tech type words bits mux romcode