Merge branch 'verilator' into masterMerge

hardware/simulation/verilator/Makefile

@@ -0,0 +1,47 @@
+ROOT_DIR:=../../..
+
+defmacro:=-D
+incdir:=-I
+
+SIM_SERVER=$(VSIM_SERVER)
+SIM_USER=$(VSIM_USER)
+SIM_PROC=Vsystem
+
+
+include ../simulation.mk
+
+# remove space between -I and directory for verilator
+INCLUDE_VERI=$(subst -I ,-I,$(INCLUDE)) 
+
+VSRC_VERI=$(subst system_tb.v,,$(VSRC))
+
+#simulator flags
+VLOG = verilator +1800-2005ext+v --error-limit 1000  -cc  $(INCLUDE_VERI) $(DEFINE) 
+#VLOG = verilator +1800-2005ext+v --error-limit 1000  -Wall -cc  $(INCLUDE2) $(DEFINE) 
+
+# Add system wrapper to the sources list to be verilated
+VSRC+=sim_system_top.v
+
+#run the simulator
+run: $(VSRC) $(VHDR) firmware boot.hex
+	$(VLOG) $(VSRC_VERI) --trace --top-module sim_system_top -Wno-WIDTH -Wno-PINMISSING -Wno-fatal --exe sim_xtop.cpp  
+	make -C obj_dir -j -f Vsim_system_top.mk Vsim_system_top
+	cp obj_dir/Vsim_system_top Vsim_system_top
+	./Vsim_system_top
+
+
+clean: hw-clean
+	mv sim_system_top.v sim_system_top.ver
+	@rm  -f *.v *.cpp *.hex Vsim_system_top
+
+sim-clean: hw-clean
+	@rm -f *.cpp Vsystem
+	@rm -rf obj_dir
+	mv sim_system_top.ver sim_system_top.v
+
+#@rm  -f *.v *.cpp *.hex Vsystem  !("sim_system_top.v")
+
+
+.PHONY: run clean
+
+

hardware/simulation/verilator/sim_system_top.v

@@ -0,0 +1,77 @@
+`timescale 1ns / 1ps
+`include "system.vh"
+//`include "cpu_nat_s_if.v"
+
+/*
+
+This is a wrapper module for verilator simulation
+that will communicate with the console and get things
+done
+
+Therefore it will be a module with inout unlike system_tb.v
+*/
+
+module sim_system_top(
+            //cpu and uart related stuff
+	          input                    clk,
+	          input                    reset,
+            output                   trap,
+
+            // Interface from cpu i.e. parallel data
+            input                    valid,
+            input [`UART_ADDR_W-1:0] addr,
+            input [`DATA_W-1:0]      wdata,
+            input [3:0]              wstrb,
+            output [`DATA_W-1:0]     rdata,
+            output                   ready
+ );
+
+   // Wires that will connect both units
+   wire iob_txd;
+   wire iob_rxd;
+   wire iob_rts; // pin with rts on iob_soc
+   wire iob_cts; // pin with cts on iob_soc
+
+
+
+system system (
+   	  .clk           (clk),
+		  .reset         (reset),
+		  .trap          (trap),
+                  //UART
+		  .uart_txd      (iob_txd),
+		  .uart_rxd      (iob_rxd),
+		  .uart_rts      (iob_rts),
+		  .uart_cts      (iob_cts)
+		  );
+
+
+iob_uart #(
+                           .ADDR_W(`UART_ADDR_W),
+                           .DATA_W(`DATA_W),
+                           .WDATA_W(`DATA_W)
+) testbench_uart
+ (
+      .clk       (clk),
+      .rst       (reset),
+      .valid     (valid),
+      .address   (addr),
+      .wdata     (wdata),
+      .wstrb     (wstrb),
+      .rdata     (rdata),
+      .ready     (ready),
+      .txd       (iob_rxd),
+      .rxd       (iob_txd),
+      .rts       (iob_cts),
+      .cts       (iob_rts)
+  );
+
+  initial begin
+
+    // configure uart
+    cpu_inituart();
+
+
+  end
+
+endmodule

hardware/testbench/sim_xtop.cpp

@@ -1,11 +1,11 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-#include "Vsystem.h"
+#include "Vsim_system_top.h"
 #include "verilated.h"
 #include "verilated_vcd_c.h"
 
-unsigned int main_time = 0; 
+unsigned int main_time = 0;
 
 double sc_time_stamp () {
   return main_time;
@@ -15,49 +15,51 @@ int main(int argc, char **argv, char **env)
 {
   Verilated::commandArgs(argc, argv);
   Verilated::traceEverOn(true);
-  Vsystem* top = new Vsystem;
+  Vsim_system_top* top = new Vsim_system_top;
   VerilatedVcdC* tfp = new VerilatedVcdC;
-  
+
   top->trace (tfp, 1);
   tfp->open ("waves.vcd");
 
+  //uart always clear to send
+  //  top->test_wire = 1;
 
-  // Reset sequence 
+  // Reset sequence
   top->clk = 0;
   top->reset = 0;
   top->eval();
   tfp->dump(main_time);
   main_time++;
-  
+
   top->clk=1;
   top->reset=0;
   top->eval();
   tfp->dump(main_time);
   main_time++;
-        
+
   top->clk=0;
   top->reset=1;
   top->eval();
   tfp->dump(main_time);
-  main_time++;        
+  main_time++;
 
   top->clk=1;
   top->reset=1;
   top->eval();
   tfp->dump(main_time);
-  main_time++;        
-  
+  main_time++;
+
   top->clk=0;
   top->reset=0;
   top->eval();
   tfp->dump(main_time);
-  main_time++; 
+  main_time++;
 
-  for (int i = 0; i<4000;i++){
+  for (int i = 0; i<20000;i++){
   top->clk ^= 1UL << 0;
   top->eval();
   tfp->dump(main_time);
-  main_time++; 
+  main_time+=10000;
   }
 
 

software/console/FIFO.py

@@ -0,0 +1,50 @@
+import os
+
+mode = 0o600
+
+class FifoFile:
+    def __init__(self, path):
+        self.path = path
+        if not os.path.exists(path):
+            os.mkfifo(path, mode)
+            print('FIFO named ' + str(path) + 'is created successfully.')
+
+    def read(self, number_of_bytes = 1):
+        i = 0
+        data = b''
+        # print(number_of_bytes)
+        with open(self.path) as fifo:
+            print("FIFO opened")
+            while(i<number_of_bytes):
+                data += bytes(fifo.read(1), 'ascii')
+                if len(data) == b'':
+                    print("Writer closed")
+                    break
+                print('Read: "{0}"'.format(data))
+                i += 1
+            return data
+
+    def read_until(self, end = b'\x00'):
+        i = 0
+        data = b''
+        # print(number_of_bytes)
+        with open(self.path) as fifo:
+            print("FIFO opened")
+            while(True):
+                data += bytes(fifo.read(1), 'ascii')
+                if len(data) == b'':
+                    print("Writer closed")
+                    break
+                print('Read: "{0}"'.format(data))
+                if (data == b'\x00'):
+                    break
+            return data
+
+    def write(self, data):
+        with open(self.path, 'wb') as fifo:
+            fifo.write(data)
+
+    def close(self):
+        os.remove(self.path)
+        print('Removed file: "{0}"'.format(self.path))
+

software/console/Makefile

@@ -2,34 +2,30 @@ ROOT_DIR:=../..
 include $(ROOT_DIR)/system.mk
 
 SERIAL:=/dev/ttyUSB0
-
-CC:=gcc
-CFLAGS:=-g -Wall
+TEST_BENCH:=0
 
 INCLUDE+=-I$(UART_DIR)/software -I$(FIRM_DIR)
 
-HDR:=console.c $(UART_DIR)/software $(FIRM_DIR)/UARTsw_reg.h
-
-SRC:=console.c rs232comm.c
+HDR:=$(UART_DIR)/software $(FIRM_DIR)/UARTsw_reg.h
 
 CONSOLE_CMD=./console -s $(SERIAL)
 ifeq ($(INIT_MEM),0)
 	CONSOLE_CMD+=-f
 endif
+ifeq ($(TEST_BENCH),1)
+	CONSOLE_CMD+=-L
+endif
 
 $(FIRM_DIR)/firmware.bin: $(FIRM_DIR)/firmware.c
 	$(eval CONSOLE_CMD+=-f)
 
 firmware.bin: $(FIRM_DIR)/firmware.bin
 	cp $(FIRM_DIR)/firmware.bin .
 
-run: firmware.bin build 
+run: firmware.bin
 	$(CONSOLE_CMD) $(TEST_LOG)
 
-build: $(HDR) $(SRC)
-	$(CC) $(CFLAGS) $(INCLUDE) $(SRC) -o console
-
 clean:
-	rm -f *# *~ console firmware.bin
+	rm -f *# *~ firmware.bin
 
-.PHONY: run build clean
+.PHONY: run clean