xtensa: Set CONFIG_DCACHE_LINE_SIZE for NXP/Intel boards used in SOF module

[LaurentiuM1234]

No description provided.

[kv2019i]

+1 for all Intel bits.

[softwarecki]

I don't understand why we need this definition? We already have defined d-cache-line-size in dt. It can be read using sys_cache_data_line_size_get()

[LaurentiuM1234]

I don't understand why we need this definition? We already have defined d-cache-line-size in dt. It can be read using sys_cache_data_line_size_get()

Sadly that can't be used in SOF as the size of the data cache line needs to be known at build time as the alignment of some data (e.g: the heap) depends on it.

[LaurentiuM1234]

Update: added CONFIG_DCACHE_LINE_SIZE for intel_adsp_ace20_lnl.

[softwarecki]

I don't understand why we need this definition? We already have defined d-cache-line-size in dt. It can be read using sys_cache_data_line_size_get()

Sadly that can't be used in SOF as the size of the data cache line needs to be known at build time as the alignment of some data (e.g: the heap) depends on it.

We can still read it from DT at build time. DT_PROP_OR(DT_PATH(cpus, cpu_0), d_cache_line_size, 0);

[LaurentiuM1234]

I don't understand why we need this definition? We already have defined d-cache-line-size in dt. It can be read using sys_cache_data_line_size_get()

Sadly that can't be used in SOF as the size of the data cache line needs to be known at build time as the alignment of some data (e.g: the heap) depends on it.

We can still read it from DT at build time. DT_PROP_OR(DT_PATH(cpus, cpu_0), d_cache_line_size, 0);

Agreed but is there a reason for which this approach is better than the current one? We'd still have to add said property to all the NXP boards and intel_adsp_ace20_lnl.

EDIT: Also seems kinda odd to query the property of a CPU you have disabled (i.e: in the case of i.MX93 which uses CPU 1 not CPU 0 which is disabled)