boards: xtensa: Set DCACHE_LINE_SIZE for all SOF-supported NXP SoCs

This commit sets the DCACHE_LINE_SIZE config for all xtensa-based NXP SoCs for SOF usage. Signed-off-by: Laurentiu Mihalcea <[email protected]>
zephyrproject-rtos · May 16, 2023 · 51eb1a1 · 51eb1a1
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commit 51eb1a1
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diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig
@@ -19,3 +19,5 @@ CONFIG_2ND_LEVEL_INTERRUPTS=n
 
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_CLEANUP_INTERMEDIATE_FILES=y
+
+CONFIG_DCACHE_LINE_SIZE=128
diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig
@@ -20,3 +20,5 @@ CONFIG_2ND_LEVEL_INTERRUPTS=n
 
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_CLEANUP_INTERMEDIATE_FILES=y
+
+CONFIG_DCACHE_LINE_SIZE=128
diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig
@@ -19,3 +19,5 @@ CONFIG_2ND_LEVEL_INTERRUPTS=n
 
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_CLEANUP_INTERMEDIATE_FILES=y
+
+CONFIG_DCACHE_LINE_SIZE=128
Original file line number	Diff line number	Diff line change
Expand Up		@@ -19,3 +19,5 @@ CONFIG_2ND_LEVEL_INTERRUPTS=n

		CONFIG_BUILD_OUTPUT_BIN=n
		CONFIG_CLEANUP_INTERMEDIATE_FILES=y

		CONFIG_DCACHE_LINE_SIZE=128
Original file line number	Diff line number	Diff line change
Expand Up		@@ -20,3 +20,5 @@ CONFIG_2ND_LEVEL_INTERRUPTS=n

		CONFIG_BUILD_OUTPUT_BIN=n
		CONFIG_CLEANUP_INTERMEDIATE_FILES=y

		CONFIG_DCACHE_LINE_SIZE=128