cAVS updates

drivers/interrupt_controller/intc_cavs.c

@@ -67,29 +67,29 @@ static void cavs_ictl_isr(const struct device *port)
 				      config->isr_table_offset);
 }
 
-static inline void cavs_ictl_irq_enable(const struct device *dev,
+static void cavs_ictl_irq_enable(const struct device *dev,
 					unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->enable_il = (1 << irq);
+	regs->enable_il = 1 << irq;
 }
 
-static inline void cavs_ictl_irq_disable(const struct device *dev,
+static void cavs_ictl_irq_disable(const struct device *dev,
 					 unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->disable_il = (1 << irq);
+	regs->disable_il = 1 << irq;
 }
 
-static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
+static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
@@ -100,11 +100,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 	 * corresponding interrupts are disabled. This function
 	 * returns 0 only if ALL the interrupts are disabled.
 	 */
-	if (regs->disable_state_il == 0xFFFFFFFF) {
-		return 0;
-	}
-
-	return 1;
+	return regs->disable_state_il != 0xFFFFFFFF;
 }
 
 static int cavs_ictl_irq_get_line_state(const struct device *dev,
@@ -132,6 +128,11 @@ static const struct irq_next_level_api cavs_apis = {
 #define CAVS_ICTL_INIT(n)						\
 	static int cavs_ictl_##n##_initialize(const struct device *port) \
 	{								\
+		struct cavs_ictl_runtime *context = port->data;		\
+		volatile struct cavs_registers * const regs =		\
+			(struct cavs_registers *)context->base_addr;	\
+		regs->disable_il = ~0;					\
+									\
 		return 0;						\
 	}								\
 									\

dts/xtensa/intel/intel_cavs25.dtsi

@@ -41,7 +41,7 @@
 	sram0: memory@be000000 {
 		device_type = "memory";
 		compatible = "mmio-sram";
-		reg = <0xbe000000 DT_SIZE_K(3008)>;
+		reg = <0xbe000000 DT_SIZE_K(1920)>;
 	};
 
 	sram1: memory@be800000 {

samples/audio/sof/boards/intel_adsp_cavs25.conf

@@ -3,4 +3,5 @@ CONFIG_INTEL_DMIC=y
 CONFIG_INTEL_SSP=y
 CONFIG_INTEL_ALH=y
 CONFIG_LP_MEMORY_BANKS=1
-CONFIG_HP_MEMORY_BANKS=46
+CONFIG_HP_MEMORY_BANKS=30
+CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h"

samples/audio/sof/prj.conf

@@ -2,6 +2,7 @@ CONFIG_SOF=y
 CONFIG_SMP=n
 CONFIG_LOG=y
 CONFIG_MP_NUM_CPUS=1
+CONFIG_BUILD_OUTPUT_BIN=n
 
 # Requires heap_info() be implemented, but no Zephyr wrapper
 CONFIG_DEBUG_MEMORY_USAGE_SCAN=n

scripts/west_commands/sign.py

@@ -420,19 +420,33 @@ def sign(self, command, build_dir, bcfg, formats):
         board = cache['CACHED_BOARD']
         log.inf('Signing for board ' + board)
         target = self.edt_get_rimage_target(board)
-        log.inf('Signing for SOC target ' + target)
+        conf = target + '.toml'
+        log.inf('Signing for SOC target ' + target + ' using ' + conf)
 
         if not args.quiet:
             log.inf('Signing with tool {}'.format(tool_path))
 
         bootloader = str(b / 'zephyr' / 'bootloader.elf.mod')
         kernel = str(b / 'zephyr' / 'zephyr.elf.mod')
         out_bin = str(b / 'zephyr' / 'zephyr.ri')
+        out_xman = str(b / 'zephyr' / 'zephyr.ri.xman')
+        out_tmp = str(b / 'zephyr' / 'zephyr.rix')
+        rimage_conf = pathlib.Path(cache['RIMAGE_CONFIG_PATH'])
+        conf_path = str(rimage_conf / conf)
 
         sign_base = ([tool_path] + args.tool_args +
-                     ['-o', out_bin, '-m', target, '-i', '3'] +
+                     ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] +
                      [bootloader, kernel])
 
         if not args.quiet:
             log.inf(quote_sh_list(sign_base))
         subprocess.check_call(sign_base)
+
+        filenames = [out_xman, out_bin]
+        with open(out_tmp, 'wb') as outfile:
+            for fname in filenames:
+                with open(fname, 'rb') as infile:
+                    outfile.write(infile.read())
+
+        os.remove(out_bin)
+        os.rename(out_tmp, out_bin)

soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h

@@ -17,13 +17,8 @@
 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
 
-#ifdef CONFIG_BOOTLOADER_MCUBOOT
-#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#else
 #define SRAM_BASE (L2_SRAM_BASE)
 #define SRAM_SIZE (L2_SRAM_SIZE)
-#endif
 
 /* The reset vector address in SRAM and its size */
 #define XCHAL_RESET_VECTOR0_PADDR_SRAM		SRAM_BASE
@@ -97,10 +92,6 @@
 /* size of the Interrupt Descriptor Table (IDT) */
 #define IDT_SIZE				0x2000
 
-/* low power ram where DMA buffers are typically placed */
-#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
-#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
-
 /* bootloader */
 
 #define HP_SRAM_BASE	0xbe000000
@@ -142,6 +133,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
@@ -218,4 +211,8 @@
 /* Host page size */
 #define HOST_PAGE_SIZE		4096
 
+/* low power ram where DMA buffers are typically placed */
+#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
+
 #endif /* __INC_MEMORY_H */

soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h

@@ -204,6 +204,7 @@
 #define SHIM_HSPGCTL		0x80
 #define SHIM_LSPGCTL		0x84
 #define SHIM_SPSREQ		0xa0
+#define LSPGCTL			(SHIM_BASE + SHIM_LSPGCTL)
 
 #define SHIM_SPSREQ_RVNNP	BIT(0)
 

soc/xtensa/intel_adsp/cavs_v15/linker.ld

@@ -25,7 +25,7 @@ OUTPUT_ARCH(xtensa)
 PROVIDE(__memctl_default = 0x00000000);
 PROVIDE(_MemErrorHandler = 0x00000000);
 
-#define LPRAM_REGION lpram
+#define LP_SRAM_REGION lpram
 
 /* DSP RAM regions (all of them) are mapped twice on the DSP: once in
  * a 512MB region from 0x80000000-0x9fffffff and again from
@@ -123,15 +123,18 @@ MEMORY
 	len = IDT_SIZE
 #endif
   lpram :
-	org = LPRAM_BASE,
-	len = LPRAM_SIZE
+	org = LP_SRAM_BASE,
+	len = LP_SRAM_SIZE
 
   static_uuid_entries_seg (!ari) :
         org = UUID_ENTRY_ELF_BASE,
         len = UUID_ENTRY_ELF_SIZE
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -161,6 +164,7 @@ PHDRS
   ucram_phdr PT_LOAD;
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
 _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -500,7 +509,7 @@ SECTIONS
     _dma_buf_start = ABSOLUTE(.);
     *(.dma_buffers)
     _dma_buf_end = ABSOLUTE(.);
-  } >LPRAM_REGION
+  } >LP_SRAM_REGION
   _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
   .comment  0 :  { *(.comment) }
   .debug 0 : { *(.debug) }
@@ -567,4 +576,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h

@@ -14,13 +14,8 @@
 #define L2_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram0)))
 #define L2_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram0)))
 
-#ifdef CONFIG_BOOTLOADER_MCUBOOT
-#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
-#else
 #define SRAM_BASE (L2_SRAM_BASE)
 #define SRAM_SIZE (L2_SRAM_SIZE)
-#endif
 
 /* The reset vector address in SRAM and its size */
 #define XCHAL_RESET_VECTOR0_PADDR_SRAM		SRAM_BASE
@@ -94,10 +89,6 @@
 /* size of the Interrupt Descriptor Table (IDT) */
 #define IDT_SIZE				0x2000
 
-/* low power ram where DMA buffers are typically placed */
-#define LPRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram1)))
-#define LPRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram1)))
-
 /* bootloader */
 
 #define HP_SRAM_BASE	0xbe000000
@@ -127,7 +118,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
@@ -139,6 +130,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
@@ -174,15 +167,22 @@
 
 /* HP SRAM windows */
 
-/* window 3 */
-#define SRAM_TRACE_BASE		0xbe000000
-#define SRAM_TRACE_SIZE		0x2000
+/* window 0 */
+#define SRAM_SW_REG_BASE	(HP_SRAM_BASE + 0x4000)
+#define SRAM_SW_REG_SIZE	0x1000
 
-#define HP_SRAM_WIN3_BASE       SRAM_TRACE_BASE
-#define HP_SRAM_WIN3_SIZE       SRAM_TRACE_SIZE
+#define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE	0x1000
+
+#define HP_SRAM_WIN0_BASE	SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE	(SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+
+/* window 1 */
+#define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
+#define SRAM_INBOX_SIZE		0x2000
 
 /* window 2 */
-#define SRAM_DEBUG_BASE		(SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
 #define SRAM_DEBUG_SIZE		0x800
 
 #define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
@@ -191,20 +191,12 @@
 #define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
 #define SRAM_STREAM_SIZE	0x1000
 
-/* window 1 */
-#define SRAM_INBOX_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_INBOX_SIZE		0x2000
-
-/* window 0 */
-#define SRAM_SW_REG_BASE	(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define SRAM_SW_REG_SIZE	0x1000
-
-#define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
-#define SRAM_OUTBOX_SIZE	0x1000
-
-#define HP_SRAM_WIN0_BASE	SRAM_SW_REG_BASE
-#define HP_SRAM_WIN0_SIZE	(SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+/* window 3 */
+#define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_TRACE_SIZE		0x2000
 
+#define HP_SRAM_WIN3_BASE       SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE       SRAM_TRACE_SIZE
 
 #define SOF_TEXT_START	0xbe010400
 
@@ -221,4 +213,8 @@
 
 #define SRAM_BANK_SIZE                  (64 * 1024)
 
+/* low power ram where DMA buffers are typically placed */
+#define LP_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram1)))
+#define LP_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram1)))
+
 #endif /* __INC_MEMORY_H */

soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h

@@ -236,10 +236,6 @@
 #define LSRMCTL			0x71D54
 #define LSPGISTS		0x71D58
 
-#define SHIM_LSPGCTL		0x50
-#define SHIM_LSPGISTS		0x58
-
-
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */