scripts: Add support for 'make debug' using Segger JLink on NXP boards #31
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Adds a new debug support script using Segger JLink and configures all NXP boards so they can use it. Tested with Segger JLink GDB server V6.14b and OpenSDA v2.1 firmware. Change-Id: Ia1b297d9c93d21db61379e22f27ae54cda3ad461 Signed-off-by: Maureen Helm <[email protected]>
nashif
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the
In progress
nashif
added
In progress
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now it works |
nashif
reviewed
May 1, 2017
| @@ -4,4 +4,6 @@ DEBUG_SCRIPT = openocd.sh | |||
| OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}" | |||
| OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}" | |||
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| export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD | |||
| JLINK_DEVICE = MK64FN1M0xxx12 | |||
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do we want to make this jlink only? OpenOCD does not seem to work with current SDK and only works with latest openocd. If it works with Jlink we might want to switch to that and document it.
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I didn't see a reason to remove the OpenOCD support. I presume we'll update the OpenOCD version in a future SDK? I've also been looking at pyOCD as another option, since that is being actively maintained for NXP devices and is open source.
About documentation, this is something I plan to work on next after these scripts are cleaned up.
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we need to add support for different flashing methods via 'make flash', right now only one is supported...
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The Segger flash tool is Windows only. I've had some success getting 'make flash' to work with pyOCD on k64 and kl25z, but I'm looking into when pyOCD can support kw41 before submitting a PR for it.
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Is there a PR for pyOCD for kw41 support?
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@galak, is there anything else needed to merge this patch? |
frasa
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fix: lis3dh: Use 8 bit temperature value in low power mode Closes zephyrproject-rtos#31 See merge request blik/embedded/zephyr!46
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In the cortex-r port we are currently using GIC as a fake cascade controller hooked to a fake parent IRQ #0. And in gic_init() we use IRQ_CONNECT() to connect this dummy IRQ. Unfortunately this value is shifted and offset when calling irq_set_priority_next_level() that tries to set the IRQ priority on a value of 0xffffffff. This value is offset again in gic_irq_set_priority() that actually sets the priority on the PPI zephyrproject-rtos#31. Fix this avoiding to set any priority for IRQ #0. Signed-off-by: Carlo Caione <[email protected]>
andrewboie
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Oct 31, 2019
In the cortex-r port we are currently using GIC as a fake cascade controller hooked to a fake parent IRQ #0. And in gic_init() we use IRQ_CONNECT() to connect this dummy IRQ. Unfortunately this value is shifted and offset when calling irq_set_priority_next_level() that tries to set the IRQ priority on a value of 0xffffffff. This value is offset again in gic_irq_set_priority() that actually sets the priority on the PPI #31. Fix this avoiding to set any priority for IRQ #0. Signed-off-by: Carlo Caione <[email protected]>
finikorg
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Dec 9, 2019
…_fixes up_squared_adsp: some misc bootloader fixes
npitre
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Oct 31, 2020
The _ldiv5() is an optimized divide-by-5 function that is smaller and
faster than the generic libgcc implementation.
Yet it can be made even smaller and faster with this replacement
implementation based on a reciprocal multiplication plus some tricks.
For example, here's the assembly from the original code on ARM:
_ldiv5:
ldr r3, [r0]
movw ip, zephyrproject-rtos#52429
ldr r1, [r0, zephyrproject-rtos#4]
movt ip, 52428
adds r3, r3, zephyrproject-rtos#2
push {r4, r5, r6, r7, lr}
mov lr, #0
adc r1, r1, lr
adds r2, lr, lr
umull r7, r6, ip, r1
lsr r6, r6, zephyrproject-rtos#2
adc r7, r6, r6
adds r2, r2, r2
adc r7, r7, r7
adds r2, r2, lr
adc r7, r7, r6
subs r3, r3, r2
sbc r7, r1, r7
lsr r2, r3, zephyrproject-rtos#3
orr r2, r2, r7, lsl zephyrproject-rtos#29
umull r2, r1, ip, r2
lsr r2, r1, zephyrproject-rtos#2
lsr r7, r1, zephyrproject-rtos#31
lsl r1, r2, zephyrproject-rtos#3
adds r4, lr, r1
adc r5, r6, r7
adds r2, r1, r1
adds r2, r2, r2
adds r2, r2, r1
subs r2, r3, r2
umull r3, r2, ip, r2
lsr r2, r2, zephyrproject-rtos#2
adds r4, r4, r2
adc r5, r5, #0
strd r4, [r0]
pop {r4, r5, r6, r7, pc}
And here's the resulting assembly with this commit applied:
_ldiv5:
push {r4, r5, r6, r7}
movw r4, zephyrproject-rtos#13107
ldr r6, [r0]
movt r4, 13107
ldr r1, [r0, zephyrproject-rtos#4]
mov r3, #0
umull r6, r7, r6, r4
add r2, r4, r4, lsl zephyrproject-rtos#1
umull r4, r5, r1, r4
adds r1, r6, r2
adc r2, r7, r2
adds ip, r6, r4
adc r1, r7, r5
adds r2, ip, r2
adc r2, r1, r3
adds r2, r4, r2
adc r3, r5, r3
strd r2, [r0]
pop {r4, r5, r6, r7}
bx lr
So we're down to 20 instructions from 36 initially, with only 2 umull
instructions instead of 3, and slightly smaller stack footprint.
Signed-off-by: Nicolas Pitre <[email protected]>
andrewboie
pushed a commit
that referenced
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Nov 9, 2020
The _ldiv5() is an optimized divide-by-5 function that is smaller and
faster than the generic libgcc implementation.
Yet it can be made even smaller and faster with this replacement
implementation based on a reciprocal multiplication plus some tricks.
For example, here's the assembly from the original code on ARM:
_ldiv5:
ldr r3, [r0]
movw ip, #52429
ldr r1, [r0, #4]
movt ip, 52428
adds r3, r3, #2
push {r4, r5, r6, r7, lr}
mov lr, #0
adc r1, r1, lr
adds r2, lr, lr
umull r7, r6, ip, r1
lsr r6, r6, #2
adc r7, r6, r6
adds r2, r2, r2
adc r7, r7, r7
adds r2, r2, lr
adc r7, r7, r6
subs r3, r3, r2
sbc r7, r1, r7
lsr r2, r3, #3
orr r2, r2, r7, lsl #29
umull r2, r1, ip, r2
lsr r2, r1, #2
lsr r7, r1, #31
lsl r1, r2, #3
adds r4, lr, r1
adc r5, r6, r7
adds r2, r1, r1
adds r2, r2, r2
adds r2, r2, r1
subs r2, r3, r2
umull r3, r2, ip, r2
lsr r2, r2, #2
adds r4, r4, r2
adc r5, r5, #0
strd r4, [r0]
pop {r4, r5, r6, r7, pc}
And here's the resulting assembly with this commit applied:
_ldiv5:
push {r4, r5, r6, r7}
movw r4, #13107
ldr r6, [r0]
movt r4, 13107
ldr r1, [r0, #4]
mov r3, #0
umull r6, r7, r6, r4
add r2, r4, r4, lsl #1
umull r4, r5, r1, r4
adds r1, r6, r2
adc r2, r7, r2
adds ip, r6, r4
adc r1, r7, r5
adds r2, ip, r2
adc r2, r1, r3
adds r2, r4, r2
adc r3, r5, r3
strd r2, [r0]
pop {r4, r5, r6, r7}
bx lr
So we're down to 20 instructions from 36 initially, with only 2 umull
instructions instead of 3, and slightly smaller stack footprint.
Signed-off-by: Nicolas Pitre <[email protected]>
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Adds a new debug support script using Segger JLink and configures all
NXP boards so they can use it. Tested with Segger JLink GDB server
V6.14b and OpenSDA v2.1 firmware.
Change-Id: Ia1b297d9c93d21db61379e22f27ae54cda3ad461
Signed-off-by: Maureen Helm [email protected]
This change is