[DRAFT] Fix Zephyr SOF support for cAVS 1.8

drivers/interrupt_controller/intc_cavs.c

@@ -67,29 +67,29 @@ static void cavs_ictl_isr(const struct device *port)
 				      config->isr_table_offset);
 }
 
-static inline void cavs_ictl_irq_enable(const struct device *dev,
+static void cavs_ictl_irq_enable(const struct device *dev,
 					unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->enable_il = (1 << irq);
+	regs->enable_il = 1 << irq;
 }
 
-static inline void cavs_ictl_irq_disable(const struct device *dev,
+static void cavs_ictl_irq_disable(const struct device *dev,
 					 unsigned int irq)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
 	volatile struct cavs_registers * const regs =
 			(struct cavs_registers *)context->base_addr;
 
-	regs->disable_il = (1 << irq);
+	regs->disable_il = 1 << irq;
 }
 
-static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
+static unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 {
 	struct cavs_ictl_runtime *context = dev->data;
 
@@ -100,11 +100,7 @@ static inline unsigned int cavs_ictl_irq_get_state(const struct device *dev)
 	 * corresponding interrupts are disabled. This function
 	 * returns 0 only if ALL the interrupts are disabled.
 	 */
-	if (regs->disable_state_il == 0xFFFFFFFF) {
-		return 0;
-	}
-
-	return 1;
+	return regs->disable_state_il != 0xFFFFFFFF;
 }
 
 static int cavs_ictl_irq_get_line_state(const struct device *dev,
@@ -132,6 +128,11 @@ static const struct irq_next_level_api cavs_apis = {
 #define CAVS_ICTL_INIT(n)						\
 	static int cavs_ictl_##n##_initialize(const struct device *port) \
 	{								\
+		struct cavs_ictl_runtime *context = port->data;		\
+		volatile struct cavs_registers * const regs =		\
+			(struct cavs_registers *)context->base_addr;	\
+		regs->disable_il = ~0;					\
+									\
 		return 0;						\
 	}								\
 									\

modules/Kconfig

@@ -22,6 +22,7 @@ source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.silabs"
 source "modules/Kconfig.simplelink"
+source "modules/Kconfig.sof"
 source "modules/Kconfig.st"
 source "modules/Kconfig.stm32"
 source "modules/Kconfig.syst"

modules/Kconfig.sof

@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOF
+	bool "Sound Open Firmware (SOF)"
+	help
+	  Build Sound Open Firmware (SOF) support.
+
+if SOF
+rsource "../../modules/audio/sof/Kconfig"
+endif

samples/audio/sof/CMakeLists.txt

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.13.1)
+
+set(sof_module $ENV{ZEPHYR_BASE}/../modules/audio/sof)
+
+# This needs to be before find_package, see
+# https://github.com/zephyrproject-rtos/zephyr/issues/24512
+set(sof_defconfigs ${sof_module}/src/arch)
+if (${BOARD} STREQUAL up_squared_adsp)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/apollolake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs18)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/cannonlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs20)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/icelake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_cavs25)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/tigerlake_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_baytrail)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/baytrail_defconfig)
+elseif (${BOARD} STREQUAL intel_adsp_broadwell)
+  set(OVERLAY_CONFIG ${sof_defconfigs}/xtensa/configs/broadwell_defconfig)
+else ()
+  set(OVERLAY_CONFIG ${sof_defconfigs}/host/configs/library_defconfig)
+  set(ARCH host)
+endif ()
+
+if (NOT DEFINED ARCH)
+  set(ARCH xtensa)
+endif ()
+
+find_package(Zephyr HINTS $ENV{ZEPHYR_BASE})
+project(sample_sof)
+
+target_sources(app PRIVATE
+    src/main.c
+  )
+
+zephyr_interface_library_named(sof_lib)
+
+zephyr_library_include_directories(app PUBLIC
+    ${sof_module}/src/arch/${ARCH}/include
+    ${sof_module}/src/include
+  )

samples/audio/sof/prj.conf

@@ -0,0 +1,5 @@
+CONFIG_SOF=y
+CONFIG_SMP=n
+CONFIG_LOG=y
+CONFIG_MP_NUM_CPUS=1
+CONFIG_BUILD_OUTPUT_BIN=n

samples/audio/sof/src/main.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include <logging/log.h>
+LOG_MODULE_REGISTER(main, LOG_LEVEL_DBG);
+
+/**
+ * Should be included from sof/schedule/task.h
+ * but triggers include chain issue
+ * FIXME
+ */
+int sof_main(int argc, char *argv[]);
+
+/**
+ * TODO: Here comes SOF initialization
+ */
+
+void main(void)
+{
+	int ret;
+
+	LOG_INF("SOF on %s", CONFIG_BOARD);
+
+	/* sof_main is actually SOF initialization */
+	ret = sof_main(0, NULL);
+	if (ret) {
+		LOG_ERR("SOF initialization failed");
+	}
+
+	LOG_INF("SOF initialized");
+}

scripts/west_commands/sign.py

@@ -420,19 +420,34 @@ def sign(self, command, build_dir, bcfg, formats):
         board = cache['CACHED_BOARD']
         log.inf('Signing for board ' + board)
         target = self.edt_get_rimage_target(board)
-        log.inf('Signing for SOC target ' + target)
+        conf = target + '.toml'
+        log.inf('Signing for SOC target ' + target + ' using ' + conf)
 
         if not args.quiet:
             log.inf('Signing with tool {}'.format(tool_path))
 
+        s = pathlib.Path(os.environ.get('ZEPHYR_BASE'))
+
         bootloader = str(b / 'zephyr' / 'bootloader.elf.mod')
         kernel = str(b / 'zephyr' / 'zephyr.elf.mod')
         out_bin = str(b / 'zephyr' / 'zephyr.ri')
+        out_xman = str(b / 'zephyr' / 'zephyr.ri.xman')
+        out_tmp = str(b / 'zephyr' / 'zephyr.rix')
+        conf_path = str(s / '..' / 'modules' / 'audio' / 'sof' / 'rimage' / 'config' / conf)
 
         sign_base = ([tool_path] + args.tool_args +
-                     ['-o', out_bin, '-m', target, '-i', '3'] +
+                     ['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] +
                      [bootloader, kernel])
 
         if not args.quiet:
             log.inf(quote_sh_list(sign_base))
         subprocess.check_call(sign_base)
+
+        filenames = [out_xman, out_bin]
+        with open(out_tmp, 'wb') as outfile:
+            for fname in filenames:
+                with open(fname, 'rb') as infile:
+                    outfile.write(infile.read())
+
+        os.remove(out_bin)
+        os.rename(out_tmp, out_bin)

soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series

@@ -14,9 +14,6 @@ config SOC
 config SMP
 	default y
 
-config MP_NUM_CPUS
-	default 2
-
 config XTENSA_TIMER
 	default n
 
@@ -55,12 +52,6 @@ config TEST_LOGGING_DEFAULTS
 	default n
 	depends on TEST
 
-config IPM_CAVS_IDC
-	default y
-
-config IPM
-	default y
-
 if LOG
 
 config LOG_PRINTK
@@ -79,6 +70,15 @@ endif # LOG
 
 if SMP
 
+config MP_NUM_CPUS
+	default 2
+
+config IPM
+       default y
+
+config IPM_CAVS_IDC
+	default y
+
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 

soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h

@@ -142,6 +142,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000

soc/xtensa/intel_adsp/cavs_v15/linker.ld

@@ -132,6 +132,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  fw_metadata_seg (!ari) :
+        org = EXT_MANIFEST_ELF_BASE,
+        len = EXT_MANIFEST_ELF_SIZE
 }
 
 PHDRS
@@ -161,6 +164,7 @@ PHDRS
   ucram_phdr PT_LOAD;
   static_uuid_entries_phdr PT_NOTE;
   static_log_entries_phdr PT_NOTE;
+  metadata_entries_phdr PT_NOTE;
 }
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
 _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
+
+_EXT_MAN_ALIGN_ = 16;
+EXTERN(ext_man_fw_ver)
+EXTERN(ext_man_cavs_config)
+
 SECTIONS
 {
 
@@ -567,4 +576,10 @@ SECTIONS
   {
     *(*.static_log*)
   } > static_log_entries_seg :static_log_entries_phdr
+
+  .fw_metadata (COPY) : ALIGN(1024)
+  {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(_EXT_MAN_ALIGN_);
+  } >fw_metadata_seg :metadata_entries_phdr
 }

soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series

@@ -11,6 +11,15 @@ config SOC
 	string
 	default "intel_cavs_18"
 
+config SMP
+       default y
+
+config XTENSA_TIMER
+	default n
+
+config CAVS_TIMER
+	default y
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 400000000 if XTENSA_TIMER
 	default 19200000 if CAVS_TIMER
@@ -56,7 +65,7 @@ config LOG_BACKEND_RB
 	default y
 
 config LOG_BACKEND_RB_MEM_BASE
-	default 0xBE000000
+	default 0xBE00A000
 
 config LOG_BACKEND_RB_MEM_SIZE
 	default 8192
@@ -68,12 +77,6 @@ if SMP
 config MP_NUM_CPUS
 	default 2
 
-config XTENSA_TIMER
-	default n
-
-config CAVS_TIMER
-	default y
-
 config IPM
 	default y
 
@@ -83,8 +86,6 @@ config IPM_CAVS_IDC
 config SCHED_IPI_SUPPORTED
 	default y if IPM_CAVS_IDC
 
-endif # SMP
-
 config IPM_INTEL_ADSP
 	default y
 	depends on IPM
@@ -94,4 +95,6 @@ config IPM_CONSOLE
 	depends on CONSOLE
 	depends on IPM
 
+endif # SMP
+
 endif

soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h

@@ -6,8 +6,6 @@
 #ifndef __INC_MEMORY_H
 #define __INC_MEMORY_H
 
-#include <cavs/cpu.h>
-
 /* L2 HP SRAM */
 #define HP_RAM_RESERVE_HEADER_SPACE		0x00010000
 
@@ -127,7 +125,7 @@
 #define BOOT_LDR_STACK_SIZE		(4 * 0x1000)
 
 /* Manifest base address in IMR - used by boot loader copy procedure. */
-#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 
 /* Manifest size (seems unused). */
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
@@ -139,6 +137,8 @@
 #define LOG_ENTRY_ELF_BASE	0x20000000
 #define LOG_ENTRY_ELF_SIZE	0x2000000
 
+#define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
+#define EXT_MANIFEST_ELF_SIZE	0x2000000
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000