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same70b: patch: Fix SMC struct naming #41

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same70b: patch: Fix SMC struct naming #41

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2de4d48
same70b: patch: Fix SmcCs struct naming.
Sep 2, 2024
f06ca0c
same70: patch: Fix SmcCs struct naming.
Sep 8, 2024
080a827
samv71: patch: Fix SmcCs struct naming
Sep 8, 2024
2527282
samv71b: patch: Fix SmcCs struct naming.
Sep 8, 2024
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1 change: 1 addition & 0 deletions asf/sam/include/same70/README
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ License Link:
https://www.apache.org/licenses/LICENSE-2.0

Patch List:
* Fix SmcCs struct naming.
* Fix the GMAC priority queue registers to match the datasheet.
* Fix GMAC_SA register name.
* Fix XDMAC_CHID register name.
Expand Down
10 changes: 5 additions & 5 deletions asf/sam/include/same70/component/smc.h
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Expand Up @@ -372,12 +372,12 @@ typedef struct {
__IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */
__IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */
__IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC MODE Register (CS_number = 0) */
} SmcCsNumber;
} SmcCs_number;

#define SMCCSNUMBER_NUMBER 4
#define SMCCS_NUMBER_NUMBER 4
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
__I uint8_t Reserved1[64];
__IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC OCMS MODE Register */
__O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC OCMS KEY1 Register */
Expand All @@ -394,11 +394,11 @@ typedef struct {
__IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */
__IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */
__IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC MODE Register (CS_number = 0) */
} SmcCsNumber;
} SmcCs_number;

/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
__I uint8_t Reserved1[64];
__IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC OCMS MODE Register */
__O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC OCMS KEY1 Register */
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1 change: 1 addition & 0 deletions asf/sam/include/same70b/README
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ License Link:
https://www.apache.org/licenses/LICENSE-2.0

Patch List:
* Fix SmcCs struct naming.
* Fix QDEC deprecated symbols.
* Fix GMAC_SA register name.
* Fix XDMAC_CHID register name.
Expand Down
10 changes: 5 additions & 5 deletions asf/sam/include/same70b/component/smc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -372,12 +372,12 @@ typedef struct {
__IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register */
__IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register */
__IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register */
} SmcCsNumber;
} SmcCs_number;

#define SMCCSNUMBER_NUMBER 4
#define SMCCS_NUMBER_NUMBER 4
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */
SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */
__I uint8_t Reserved1[64];
__IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */
__O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand All @@ -394,11 +394,11 @@ typedef struct {
__IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register */
__IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register */
__IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register */
} SmcCsNumber;
} SmcCs_number;

/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register */
SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register */
__I uint8_t Reserved1[64];
__IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */
__O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand Down
1 change: 1 addition & 0 deletions asf/sam/include/samv71/README
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Original file line number Diff line number Diff line change
Expand Up @@ -39,5 +39,6 @@ License Link:
https://www.apache.org/licenses/LICENSE-2.0

Patch List:
* Fix SmcCs struct naming.
* Fix the GMAC priority queue registers to match the datasheet.
* Fix XDMAC_CHID register name.
10 changes: 5 additions & 5 deletions asf/sam/include/samv71/component/smc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -399,12 +399,12 @@ typedef struct {
__IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */
__IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */
__IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register (CS_number = 0) */
} SmcCsNumber;
} SmcCs_number;

#define SMCCSNUMBER_NUMBER 4
#define SMCCS_NUMBER_NUMBER 4
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SmcCsNumber[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
__I uint8_t Reserved1[64];
__IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */
__O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand All @@ -423,11 +423,11 @@ typedef struct {
__IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */
__IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */
__IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register (CS_number = 0) */
} SmcCsNumber;
} SmcCs_number;

/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SmcCsNumber[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
__I uint8_t Reserved1[64];
__IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */
__O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand Down
1 change: 1 addition & 0 deletions asf/sam/include/samv71b/README
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Original file line number Diff line number Diff line change
Expand Up @@ -39,5 +39,6 @@ License Link:
https://www.apache.org/licenses/LICENSE-2.0

Patch List:
* Fix SmcCs struct naming.
* Fix QDEC deprecated symbols.
* Fix XDMAC_CHID register name.
10 changes: 5 additions & 5 deletions asf/sam/include/samv71b/component/smc.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -372,12 +372,12 @@ typedef struct {
__IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register */
__IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register */
__IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register */
} SmcCsNumber;
} SmcCs_number;

#define SMCCSNUMBER_NUMBER 4
#define SMCCS_NUMBER_NUMBER 4
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SmcCsNumber[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */
SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */
__I uint8_t Reserved1[64];
__IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */
__O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand All @@ -394,11 +394,11 @@ typedef struct {
__IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register */
__IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register */
__IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register */
} SmcCsNumber;
} SmcCs_number;

/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SmcCsNumber[4]; /**< Offset: 0x00 SMC Setup Register */
SmcCs_number SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register */
__I uint8_t Reserved1[64];
__IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */
__O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */
Expand Down
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