Add support for STM32C0 #286

billphipps · 2023-03-09T18:00:09Z

Supports STM32C0x0/STM32C0x1.

Tested build configurations:

With RSA2048 and SHA2-256 the code size is 9724 and it boots in under 1 second.
With ED25519 and SHA2-384 the code size is 10024 and takes about 10 seconds for the LED to turn on.

billphipps · 2023-03-13T19:09:33Z

Still in debug mode so wolf boot is big. I'll cleanup documentation to handle debug layout and release layout. Might be able to get wolfBoot into 5 sectors if we change to SHA384, like Daniele recommends.

This build should be suitable for the demo. Takes right at 45 seconds from reset to boot app. I'll continue to clean things up.

dgarske

It works! With ED25519 and SHA2-384 the code size is 10840 and takes about 10 seconds for the LED to turn on.

I also tested with RSA2048 with SHA2-256 the code size is 13092 and it boots in under 1 second.

SIGN?=RSA2048
HASH?=SHA256

Please add these size/boot time details to the Targets.md.

dgarske · 2023-03-14T04:58:36Z

docs/Targets.md

+```
+
+### Building STM32C0
+xxx


Remove the xxx.

dgarske · 2023-03-14T04:58:57Z

docs/Targets.md

+For RAMFUNCTION support (required for SEC_PROT) make sure `RAM_CODE=1`.
+
+### STM32C0 Programming
+xxx


Remove the xxx

dgarske · 2023-03-14T04:59:02Z

docs/Targets.md

+```
+
+### STM32C0 Debugging
+xxx


Remove the xxx

dgarske · 2023-03-14T05:00:18Z

docs/Targets.md

+
+### Building STM32C0
+xxx
+Reference configuration (see [/config/examples/stm32g0.config](/config/examples/stm32g0.config)).


Replace stm32g0 with stm32c0 throughout new section.

dgarske · 2023-03-14T05:02:41Z

config/examples/stm32c0.config

+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+#Max APP size is 4kB


I think this is correct, as in NVM_FLASH_WRITEONCE the last two sectors are reserved

dgarske · 2023-03-14T05:07:37Z

hal/stm32c0.c

+    RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
+    DMB();
+
+    #if 0


Remove or comment on #if 0

hal/stm32c0.c

dgarske · 2023-03-14T05:09:30Z

hal/stm32c0.ld

+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
+    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002FFF


Might consider 12K instead of 0x00002FFF for readability.

dgarske · 2023-03-14T05:10:00Z

test-app/app_stm32c0.c

@@ -0,0 +1,39 @@
+/* main.c


app_stm32c0.c

hal/stm32c0.c

dgarske · 2023-03-14T06:32:56Z

test-app/led.c

@@ -146,6 +146,43 @@ void boot_led_on(void)

 #endif /** PLATFORM_stm32g0 **/

+#ifdef PLATFORM_stm32c0


At quick glance is identical to the above PLATFORM_stm32g0 section. I am okay with reusing the same code for both. #if defined(PLATFORM_stm32g0) || defined(PLATFORM_stm32c0). Looks like it ended up being GPIOA5 for both.

test-app/Makefile

dgarske · 2023-03-14T06:36:46Z

docs/HAL.md

@@ -19,7 +19,7 @@ and RAM boundaries.
 ## Supported platforms

 The following platforms are supported in the current version:
-  - STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0
+  - STM32F4, STM32L5, STM32L0, STM32F7, STM32H7, STM32G0, STM32C0


Since updating the list also includes: STM32WB55 and STM32U5

dgarske · 2023-03-14T06:38:45Z

docs/Targets.md

+#define WOLFBOOT_PARTITION_BOOT_ADDRESS      0x08004000 /* offset 16kB to 24kB */
+#define WOLFBOOT_PARTITION_SIZE              0x2000  /* 8 KB */
+#define WOLFBOOT_PARTITION_UPDATE_ADDRESS    0x08006000 /* offset 24kB to 32kB */
+#define WOLFBOOT_PARTITION_SWAP_ADDRESS      0x08003800 /* offset 14kB to 16kB */


I assume you resolved the issue with using the end of flash and it was related to NVM_FLASH_WRITEONCE?

Can't prove that yet. One of the things I need to test. I'll make a maximum-sized test app to prove it out.

dgarske · 2023-03-14T06:40:15Z

hal/stm32c0.c

+#   error "wolfBoot STM32C0 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
+#endif
+
+/* XXX Debug only! */


Use #ifdef DEBUG

dgarske · 2023-03-14T06:45:13Z

config/examples/stm32c0.config

+WOLFBOOT_VERSION?=0
+V?=0
+SPMATH?=1
+RAM_CODE?=1


Note: With RAM_CODE?=0 the code size is about 670 bytes smaller. However that prevents wolfBoot from having the ability to self-update. Also its about 75% slower. Recommend the default stays enabled, but might be worth documenting.

OTOH immutable wolfboot if that smaller would allow for larger partition and a better geometry (10K wolfBoot, 10K partition size, BOOT=0x08002800 UPDATE=0x08005000 SWAP=0x08007800 with 6KB max effective application size and 2 sectors reserved for NVM_FLASH_WRITEONCE in each partition)

Is the speed impact due to the code running out of the flash? I thought this had an instruction cache (small), but no data cache. I'll extend the documentation to provide those tradeoffs. Is the ONLY thing I need to do to disable wolfBoot updates is set RAM_CODE=0? Seems like we should be ok with pushing a bunch of the code into RAM during boot since the ram will be recovered during the app boot.

…r either RSA2048 or ED25519. Partition scheme allows 10KB application partition or (6KB actual due to NVM write once). Made space using NO_MPU=1, RAM_CODE=0, USE_SLOW_SHA256 and !FLASH_SECURABLE_MEMORY_SUPPORT.

dgarske · 2023-10-09T20:07:31Z

@danielinux rebased, cleaned up and improved PR. After CI it is ready for review and inclusion in upcoming release.

hal/stm32c0.c

danielinux · 2023-10-12T13:04:57Z

hal/stm32c0.c

+static void clock_pll_on(int powersave)
+{
+    uint32_t reg32;
+    uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre, flash_waitstates;


Remove declarations of unused variables (cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre)

hal/stm32c0.c

danielinux · 2023-10-12T13:24:04Z

hal/stm32c0.c

+#define RCC_CR              (*(volatile uint32_t *)(RCC_BASE + 0x00))  /* RM0444 - 5.4.1 */
+#define RCC_CFGR            (*(volatile uint32_t *)(RCC_BASE + 0x08))  /* RM0444 - 5.4.3 */


Wrong reference manual in comments - should be RM0490

danielinux · 2023-10-12T13:25:34Z

hal/stm32c0.c

+#define RCC_CFGR_SW_PLL             0x2
+#define RCC_PLLCFGR_PLLR_EN       (1 << 28) /* RM0444 - 5.4.3 */
+
+#define RCC_PLLCFGR_PLLSRC_HSI16  2


Unused PLL defines

danielinux · 2023-10-12T13:25:48Z

hal/stm32c0.c

+
+/*** FLASH ***/
+#define PWR_APB1_CLOCK_ER_VAL       (1 << 28)
+#define SYSCFG_APB2_CLOCK_ER_VAL    (1 << 0) /* RM0444 - 5.4.15 - RCC_APBENR2 - SYSCFGEN */


correct value, wrong RM in comment

danielinux · 2023-10-12T13:26:58Z

hal/stm32c0.ld

+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
+    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K-1


remove "-1"

dgarske self-requested a review March 9, 2023 20:14

dgarske assigned dgarske and billphipps Mar 9, 2023

billphipps assigned danielinux Mar 13, 2023

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dgarske changed the title ~~Add support for stm32 c0~~ Add support for STM32C0 Mar 14, 2023

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dgarske removed their assignment Jun 27, 2023

billphipps and others added 2 commits October 9, 2023 11:07

STM32C0 support

241a154

PR cleanups based on peer review. Fixes to support < 10KB wolfBoot fo…

696e655

…r either RSA2048 or ED25519. Partition scheme allows 10KB application partition or (6KB actual due to NVM write once). Made space using NO_MPU=1, RAM_CODE=0, USE_SLOW_SHA256 and !FLASH_SECURABLE_MEMORY_SUPPORT.

dgarske force-pushed the AddSupportForSTM32C0 branch from fb61bd3 to 696e655 Compare October 9, 2023 20:06

dgarske marked this pull request as ready for review October 9, 2023 20:06

dgarske previously approved these changes Oct 9, 2023

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dgarske requested a review from danielinux October 9, 2023 20:06

dgarske unassigned billphipps Oct 9, 2023

Improve C0/G0 secure hide protection feature documentation.

cd62fae

dgarske dismissed their stale review via cd62fae October 9, 2023 20:26

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Peer review cleanups and added CI test.

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dgarske requested a review from danielinux October 12, 2023 21:30

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danielinux merged commit 8d882bc into wolfSSL:master Oct 13, 2023
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Add support for STM32C0 #286

Add support for STM32C0 #286

billphipps commented Mar 9, 2023 •

edited by dgarske

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		@@ -146,6 +146,43 @@ void boot_led_on(void)

		#endif / PLATFORM_stm32g0 /

		#ifdef PLATFORM_stm32c0

		#define RCC_CR ((volatile uint32_t )(RCC_BASE + 0x00)) /* RM0444 - 5.4.1 */
		#define RCC_CFGR ((volatile uint32_t )(RCC_BASE + 0x08)) /* RM0444 - 5.4.3 */

Add support for STM32C0 #286

Add support for STM32C0 #286

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billphipps commented Mar 9, 2023 • edited by dgarske Loading

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billphipps commented Mar 9, 2023 •

edited by dgarske

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