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Fixes for CPLD and setting QE clock.
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@dgarske
dgarske committed Nov 14, 2023
1 parent aace337 commit f703290
Showing 1 changed file with 67 additions and 42 deletions.
109 changes: 67 additions & 42 deletions hal/nxp_t1024.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
#include "fdt.h"

/* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */
/* IFC: CS0 NOR, CS1 MRAM, CS2 CPLD, CS3, MPU CPLD */
/* IFC: CS0 NOR, CS1 MRAM, CS2 APU CPLD, CS3, MPU CPLD */
/* DDR: DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - SPD on I2C1 at Addr 0x51 */

/* Debugging */
Expand Down Expand Up @@ -101,6 +101,13 @@ static void hal_flash_unlock_sector(uint32_t sector);
#define DCFG_BRR ((volatile uint32_t*)(DCFG_BASE + 0xE4UL)) /* Boot Release Register (DCFG_CCSR_BRR) */
#define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */

/* SCGG (Supplemental Configuration Unit) T1024RM 6.1 */
#define SCFG_BASE (CCSRBAR + 0xFC000)
#define SCFG_QEIOCLKCR ((volatile uint32_t*)(DCFG_BASE + 0x400UL))

#define SCFG_QEIOCLKCR_CLK11 0x04000000 /* IO_CLK[11] = GPIO_4[16] */


/* T1024RM: 4.6.5 */
#define CLOCKING_BASE (CCSRBAR + 0xE1000)
#define CLOCKING_PLLPGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC00UL)) /* Platform PLL general status register */
Expand Down Expand Up @@ -433,25 +440,26 @@ enum ifc_amask_sizes {
#endif


/* CPLD */
/* CPLD (APU) */
#define CPLD_BASE 0xFFDF0000
#define CPLD_BASE_PHYS_HIGH 0xFULL

#define CPLD_VER 0x00 /* CPLD Major Revision Register */
#define CPLD_VER_SUB 0x01 /* CPLD Minor Revision Register */
#define HW_VER 0x02 /* Hardware Revision Register */
#define SW_VER 0x03 /* Software Revision register */
#define RESET_CTL1 0x10 /* Reset control Register1 */
#define RESET_CTL2 0x11 /* Reset control Register2 */
#define INT_STATUS 0x12 /* Interrupt status Register */
#define FLASH_CSR 0x13 /* Flash control and status register */
#define FAN_CTL_STATUS 0x14 /* Fan control and status register */
#define LED_CTL_STATUS 0x15 /* LED control and status register */
#define SFP_CTL_STATUS 0x16 /* SFP control and status register */
#define MISC_CTL_STATUS 0x17 /* Miscellanies ctrl & status register*/
#define BOOT_OVERRIDE 0x18 /* Boot override register */
#define BOOT_CONFIG1 0x19 /* Boot config override register*/
#define BOOT_CONFIG2 0x1A /* Boot config override register*/
/* CPLD (MPU) */
#define CPLD_MPU_BASE 0xFFCF0000
#define CPLD_MPU_BASE_PHYS_HIGH 0xFULL

#define BOARD_ID_L_ADDR 0x0002
#define BOARD_ID_H_ADDR 0x0004
#define PLD_VER_ADDR 0x0006
#define POWER_STATUS_ADDRR 0x0400
#define MPU_INT_STATUS_ADDR 0x0402
#define MPU_INT_ENABLE_ADDR 0x0404
#define MPU_CONTROL_ADDR 0x042E
#define MPU_RESET_ADDR 0x0430
#define PCI_STATUS_ADDR 0x0432
#define HS_CSR_ADDR 0x103C
#define CPCI_GA_ADDRS 0x103E
#define CPCI_INTX_ADDR 0x1040
#define PLD_CURRENT_VERSION 0x1042

#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
Expand All @@ -466,7 +474,7 @@ enum ifc_amask_sizes {
#define CPLD_OVERRIDE_BOOT_EN 0x01
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */

#define CPLD_DATA(n) ((volatile uint8_t*)(CPLD_BASE + n))
#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + n))


/* DDR4 - 2GB */
Expand Down Expand Up @@ -1116,46 +1124,60 @@ static int hal_pcie_init(void)
}
#endif

static void hal_cpld_init(void)
{
#ifdef ENABLE_CPLD
#ifdef DEBUG
uint32_t fw;
#endif
static void hal_cpld_ifc_init(uint32_t base, uint32_t base_high, uint8_t ifc)
{
/* CPLD IFC Timing Parameters */
set32(IFC_FTIM0(2), (IFC_FTIM0_GPCM_TACSE(14UL) |
set32(IFC_FTIM0(ifc), (IFC_FTIM0_GPCM_TACSE(14UL) |
IFC_FTIM0_GPCM_TEADC(14UL) |
IFC_FTIM0_GPCM_TEAHC(14UL)));
set32(IFC_FTIM1(2), (IFC_FTIM1_GPCM_TACO(14UL) |
set32(IFC_FTIM1(ifc), (IFC_FTIM1_GPCM_TACO(14UL) |
IFC_FTIM1_GPCM_TRAD(31UL)));
set32(IFC_FTIM2(2), (IFC_FTIM2_GPCM_TCS(14UL) |
set32(IFC_FTIM2(ifc), (IFC_FTIM2_GPCM_TCS(14UL) |
IFC_FTIM2_GPCM_TCH(8UL) |
IFC_FTIM2_GPCM_TWP(31UL)));
set32(IFC_FTIM3(2), 0);
set32(IFC_FTIM3(ifc), 0);

/* CPLD IFC Definitions (CS2) */
set32(IFC_CSPR_EXT(2), CPLD_BASE_PHYS_HIGH);
set32(IFC_CSPR(2), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
set32(IFC_CSPR_EXT(ifc), base_high);
set32(IFC_CSPR(ifc), (IFC_CSPR_PHYS_ADDR(base) |
IFC_CSPR_PORT_SIZE_8 |
IFC_CSPR_MSEL_GPCM |
IFC_CSPR_V));
set32(IFC_AMASK(2), IFC_AMASK_64KB);
set32(IFC_CSOR(2), 0);

/* IFC - CPLD */
set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
LAW_TRGT_IFC, LAW_SIZE_64KB, 1);
set32(IFC_AMASK(ifc), IFC_AMASK_64KB);
set32(IFC_CSOR(ifc), 0);
}
#endif
static void hal_cpld_init(void)
{
#ifdef ENABLE_CPLD
#ifdef DEBUG
uint32_t fw;
#endif

/* CPLD - TBL=1, Entry 11 */
/* CPLD (APU) IFC 2 - LAW 2, TLB 1.11 */
hal_cpld_ifc_init(CPLD_BASE, CPLD_BASE_PHYS_HIGH, 2);
set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, LAW_TRGT_IFC, LAW_SIZE_64KB, 1);
set_tlb(1, 11, CPLD_BASE,
CPLD_BASE, CPLD_BASE_PHYS_HIGH,
(MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1);
(MAS3_SX | MAS3_SW | MAS3_SR),
(MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1);

/* CPLD (MPU) IFC 3 - LAW 6, TLB 1.10 */
hal_cpld_ifc_init(CPLD_MPU_BASE, CPLD_MPU_BASE_PHYS_HIGH, 3);
set_law(6, CPLD_MPU_BASE_PHYS_HIGH, CPLD_MPU_BASE, LAW_TRGT_IFC,
LAW_SIZE_64KB, 1);
set_tlb(1, 10, CPLD_MPU_BASE,
CPLD_MPU_BASE, CPLD_MPU_BASE_PHYS_HIGH,
(MAS3_SX | MAS3_SW | MAS3_SR),
(MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1);

#ifdef DEBUG
fw = get8(CPLD_DATA(HW_VER));
wolfBoot_printf("CPLD HW Rev: 0x%x\n", fw);
fw = get8(CPLD_DATA(SW_VER));
wolfBoot_printf("CPLD SW Rev: 0x%x\n", fw);
fw = get16(CPLD_DATA(BOARD_ID_L_ADDR)) << 16;
fw |= get16(CPLD_DATA(BOARD_ID_H_ADDR));
wolfBoot_printf("CPLD BOARD_ID: 0x%x\n", fw);
fw = get16(CPLD_DATA(PLD_VER_ADDR));
wolfBoot_printf("CPLD PLD_VER: 0x%x\n", fw);
#endif
#endif /* ENABLE_CPLD */
}
Expand Down Expand Up @@ -1358,6 +1380,9 @@ static int hal_qe_init(void)
uint32_t sdma_base;
const struct qe_firmware* fw = (const struct qe_firmware*)QE_FW_ADDR;

/* setup QE clk */
set32(SCFG_QEIOCLKCR, get32(SCFG_QEIOCLKCR) | SCFG_QEIOCLKCR_CLK11);

ret = qe_check_firmware(fw, "QE");
if (ret == 0) {
/* Upload microcode to IRAM */
Expand Down

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