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Fix upper real page number from c code. Relocate to upper regions CCS…
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…RBAR, Flash and CPLD. Cleanups for readability.
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dgarske committed Sep 26, 2023
1 parent d80c6fa commit d62210a
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Showing 7 changed files with 95 additions and 94 deletions.
14 changes: 7 additions & 7 deletions hal/nxp_p1021.c
Original file line number Diff line number Diff line change
Expand Up @@ -992,18 +992,18 @@ static int hal_pcie_init(void)
set_law(3, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB),

/* Map TLB for PCIe */
set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
set_tlb(1, 3, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
(CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
(CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000), 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
set_tlb(1, 5, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);

set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);
return 0;
}
Expand All @@ -1016,7 +1016,7 @@ static int hal_cpld_init(void)
/* Setup Local Access Window (LAW) for CPLD/BCSR */
set_law(5, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB);
/* Setup TLB MMU (Translation Lookaside Buffer) for CPLD/BCSR */
set_tlb(1, 8, BCSR_BASE, BCSR_BASE, MAS3_SX | MAS3_SW | MAS3_SR,
set_tlb(1, 8, BCSR_BASE, BCSR_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR,
MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);

/* setup eLBC for CPLD (CS1), 8-bit */
Expand Down Expand Up @@ -1509,7 +1509,7 @@ static void hal_mp_init(void)

/* map reset page to bootpg so we can copy code there */
disable_tlb1(i_tlb);
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */

Expand Down
21 changes: 10 additions & 11 deletions hal/nxp_ppc.h
Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@
#define CCSRBAR_SIZE BOOKE_PAGESZ_16M

/* relocate to 64-bit 0xF_ */
//#define CCSRBAR_PHYS_HIGH 0xF
//#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
#define CCSRBAR_PHYS_HIGH 0xFULL
#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)

#define ENABLE_L1_CACHE
#define ENABLE_L2_CACHE
Expand All @@ -80,7 +80,7 @@
#define ENABLE_DDR

#define FLASH_BASE_ADDR 0xEC000000
#define FLASH_BASE_PHYS_HIGH 0x0
#define FLASH_BASE_PHYS_HIGH 0xFULL
#define FLASH_LAW_SIZE LAW_SIZE_64MB
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M

Expand All @@ -96,7 +96,7 @@
#define CCSRBAR_SIZE BOOKE_PAGESZ_16M

/* relocate to 64-bit 0xE_ */
//#define CCSRBAR_PHYS_HIGH 0xE
//#define CCSRBAR_PHYS_HIGH 0xEULL
//#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)

#define ENABLE_L1_CACHE
Expand All @@ -108,7 +108,7 @@
#define ENABLE_DDR

#define FLASH_BASE_ADDR 0xE8000000
#define FLASH_BASE_PHYS_HIGH 0x0
#define FLASH_BASE_PHYS_HIGH 0x0ULL
#define FLASH_LAW_SIZE LAW_SIZE_128MB
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M

Expand Down Expand Up @@ -141,7 +141,7 @@
#define CCSRBAR_PHYS CCSRBAR
#endif
#ifndef CCSRBAR_PHYS_HIGH
#define CCSRBAR_PHYS_HIGH 0
#define CCSRBAR_PHYS_HIGH 0ULL
#endif

/* DDR */
Expand Down Expand Up @@ -519,8 +519,7 @@
(((epn) & MAS2_EPN) | (wimge))
#define BOOKE_MAS3(rpn, user, perms) \
(((rpn) & MAS3_RPN) | (user) | (perms))
#define BOOKE_MAS7(rpn) \
(((unsigned long long)(rpn) >> 32) & MAS7_RPN)
#define BOOKE_MAS7(urpn) (urpn)

/* Stringification */
#ifndef WC_STRINGIFY
Expand All @@ -536,7 +535,6 @@
})
#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))

#define GET_PHYS_HIGH(addr) (((uint64_t)(addr)) >> 32)

#ifndef __ASSEMBLER__

Expand Down Expand Up @@ -605,8 +603,9 @@ static inline void set32(volatile unsigned int *addr, unsigned int val)
}

/* C version in boot_ppc.c */
extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize, uint8_t iprot);
extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn,
uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize,
uint8_t iprot);
extern void disable_tlb1(uint8_t esel);
extern void flush_cache(uint32_t start_addr, uint32_t size);

Expand Down
30 changes: 14 additions & 16 deletions hal/nxp_t1024.c
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@

/* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */
/* IFC: CS0 NOR, CS1 MRAM, CS2 CPLD, CS3, MPU CPLD */
/* DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - I2C1 SPD Addr 0x51 */
/* DDR: DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - SPD on I2C1 at Addr 0x51 */

/* Tests */
#if 1
Expand Down Expand Up @@ -261,7 +261,7 @@ static int test_tpm(void);
#define IFC_FTIM2(n) ((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30)))
#define IFC_FTIM3(n) ((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30)))

#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */
#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFFFF00) /* Physical base address */
#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */
#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */
#define IFC_CSPR_WP 0x00000040 /* Write Protect */
Expand Down Expand Up @@ -316,8 +316,6 @@ enum ifc_amask_sizes {


/* NOR Flash */
#define FLASH_BASE 0xEC000000

#define FLASH_BANK_SIZE (64*1024*1024)
#define FLASH_PAGE_SIZE (1024) /* program buffer */
#define FLASH_SECTOR_SIZE (128*1024)
Expand Down Expand Up @@ -361,7 +359,7 @@ enum ifc_amask_sizes {

/* CPLD */
#define CPLD_BASE 0xFFDF0000
#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE)
#define CPLD_BASE_PHYS_HIGH 0xFULL

#define CPLD_VER 0x00 /* CPLD Major Revision Register */
#define CPLD_VER_SUB 0x01 /* CPLD Minor Revision Register */
Expand Down Expand Up @@ -754,7 +752,7 @@ void uart_write(const char* buf, uint32_t sz)
#if 0
static void* hal_flash_map(uintptr_t sect, uintptr_t offset)
{
uint8_t* ptr = FLASH_BASE;
uint8_t* ptr = FLASH_BASE_ADDR;

#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)
#define FLASH_CFI_16BIT 0x02 /* word */
Expand Down Expand Up @@ -784,15 +782,15 @@ static void hal_flash_init(void)
set32(IFC_FTIM3(0), 0);
/* NOR IFC Definitions (CS0) */
set32(IFC_CSPR_EXT(0), FLASH_BASE_PHYS_HIGH);
set32(IFC_CSPR(0), (IFC_CSPR_PHYS_ADDR(FLASH_BASE) | \
set32(IFC_CSPR(0), (IFC_CSPR_PHYS_ADDR(FLASH_BASE_ADDR) | \
IFC_CSPR_PORT_SIZE_16 | \
IFC_CSPR_MSEL_NOR | \
IFC_CSPR_V));
set32(IFC_AMASK(0), IFC_AMASK_64MB);
set32(IFC_CSOR(0), 0x0000000C); /* TRHZ (80 clocks for read enable high) */

/* Get Manufacture ID */
#define FLASH_IO16(n) *((volatile uint16_t*)(FLASH_BASE + (n)))
#define FLASH_IO16(n) *((volatile uint16_t*)(FLASH_BASE_ADDR + (n)))

FLASH_IO16(0) = (((uint16_t)FLASH_CMD_RESET) << 8);
udelay(1);
Expand All @@ -815,7 +813,7 @@ static void hal_ddr_init(void)
}

/* Map LAW for DDR */
set_law(15, DDR_ADDRESS, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB);
set_law(15, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB);

/* Set early for clock / pin */
set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL);
Expand Down Expand Up @@ -936,10 +934,10 @@ static void hal_ddr_init(void)
#endif

/* DDR - TBL=1, Entry 12/13 */
set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS,
set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
0, BOOKE_PAGESZ_1G, 1);
set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000,
set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, 0,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
0, BOOKE_PAGESZ_1G, 1);
#endif
Expand Down Expand Up @@ -990,7 +988,7 @@ static void hal_cpld_init(void)
set32(IFC_FTIM3(2), 0);

/* CPLD IFC Definitions (CS2) */
set32(IFC_CSPR_EXT(2), GET_PHYS_HIGH(CPLD_BASE_PHYS));
set32(IFC_CSPR_EXT(2), CPLD_BASE_PHYS_HIGH);
set32(IFC_CSPR(2), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
IFC_CSPR_PORT_SIZE_8 |
IFC_CSPR_MSEL_GPCM |
Expand All @@ -999,11 +997,11 @@ static void hal_cpld_init(void)
set32(IFC_CSOR(2), 0);

/* IFC - CPLD */
set_law(2, GET_PHYS_HIGH(CPLD_BASE_PHYS), CPLD_BASE,
set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
LAW_TRGT_IFC, LAW_SIZE_4KB);

/* CPLD - TBL=1, Entry 11 */
set_tlb(1, 11, CPLD_BASE, CPLD_BASE_PHYS,
set_tlb(1, 11, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, BOOKE_PAGESZ_4K, 1);

Expand Down Expand Up @@ -1337,7 +1335,7 @@ static void hal_mp_init(void)

/* map reset page to bootpg so we can copy code there */
disable_tlb1(i_tlb);
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn, urpn */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */

Expand Down Expand Up @@ -1500,7 +1498,7 @@ static int test_flash(void)
{
int ret;
uint32_t i;
uint8_t* pagePtr = (uint8_t*)FLASH_BASE + TEST_ADDRESS;
uint8_t* pagePtr = (uint8_t*)FLASH_BASE_ADDR + TEST_ADDRESS;

#ifndef TEST_FLASH_READONLY
/* Erase sector */
Expand Down
10 changes: 5 additions & 5 deletions hal/nxp_t2080.c
Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@ enum ifc_amask_sizes {
#endif
/* CPLD */
#define CPLD_BASE 0xFFDF0000
#define CPLD_BASE_PHYS (0xF00000000ULL | CPLD_BASE)
#define CPLD_BASE_PHYS_HIGH 0xFULL

#define CPLD_SPARE 0x00
#define CPLD_SATA_MUX_SEL 0x02
Expand Down Expand Up @@ -458,7 +458,7 @@ static void hal_ddr_init(void)
while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG_2_D_INIT));

/* DDR - TBL=1, Entry 19 */
set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS,
set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS, 0,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, BOOKE_PAGESZ_2G, 1);
#endif
Expand All @@ -484,7 +484,7 @@ static void hal_cpld_init(void)
IFC_FTIM3(3) = 0;

/* CPLD IFC Definitions (CS3) */
IFC_CSPR_EXT(3) = (0xF);
IFC_CSPR_EXT(3) = CPLD_BASE_PHYS_HIGH;
IFC_CSPR(3) = (IFC_CSPR_PHYS_ADDR(CPLD_BASE) |
IFC_CSPR_PORT_SIZE_16 |
IFC_CSPR_MSEL_GPCM |
Expand All @@ -493,11 +493,11 @@ static void hal_cpld_init(void)
IFC_CSOR(3) = 0;

/* IFC - CPLD */
set_law(2, GET_PHYS_HIGH(CPLD_BASE_PHYS), CPLD_BASE,
set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
LAW_TRGT_IFC, LAW_SIZE_4KB);

/* CPLD - TBL=1, Entry 17 */
set_tlb(1, 17, CPLD_BASE, CPLD_BASE_PHYS,
set_tlb(1, 17, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, BOOKE_PAGESZ_4K, 1);
#endif
Expand Down
16 changes: 10 additions & 6 deletions src/boot_ppc.c
Original file line number Diff line number Diff line change
Expand Up @@ -46,17 +46,17 @@ void write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3,
asm volatile("isync;msync;tlbwe;isync");
}

void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint64_t rpn,
uint8_t perms, uint8_t wimge,
uint8_t ts, uint8_t tsize, uint8_t iprot)
void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn,
uint32_t urpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t tsize,
uint8_t iprot)
{
uint32_t _mas0, _mas1, _mas2, _mas3, _mas7;

_mas0 = BOOKE_MAS0(tlb, esel, 0);
_mas1 = BOOKE_MAS1(1, iprot, 0, ts, tsize);
_mas2 = BOOKE_MAS2(epn, wimge);
_mas3 = BOOKE_MAS3(rpn, 0, perms);
_mas7 = BOOKE_MAS7(rpn);
_mas7 = BOOKE_MAS7(urpn);

write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
}
Expand Down Expand Up @@ -146,11 +146,11 @@ void do_boot(const uint32_t *app_offset, const uint32_t* dts_offset)
void do_boot(const uint32_t *app_offset)
#endif
{
typedef void (*boot_entry)(uintptr_t r3, uintptr_t r4, uintptr_t r5, uintptr_t r6,
uintptr_t r7, uintptr_t r8, uintptr_t r9);
#ifndef BUILD_LOADER_STAGE1
uint32_t msr;
#endif
typedef void (*boot_entry)(uintptr_t r3, uintptr_t r4, uintptr_t r5, uintptr_t r6,
uintptr_t r7, uintptr_t r8, uintptr_t r9);
boot_entry entry = (boot_entry)app_offset;

#ifndef BUILD_LOADER_STAGE1
Expand All @@ -167,7 +167,11 @@ void do_boot(const uint32_t *app_offset)
* https://elinux.org/images/c/cf/Power_ePAPR_APPROVED_v1.1.pdf
*/
entry(
#ifdef MMU
(uintptr_t)dts_offset, /* r3 = dts address */
#else
0,
#endif
0, 0,
EPAPR_MAGIC, /* r6 = ePAPR magic */
WOLFBOOT_PARTITION_SIZE, /* r7 = Size of Initial Mapped Area (IMA) */
Expand Down
12 changes: 6 additions & 6 deletions src/boot_ppc_mp.S
Original file line number Diff line number Diff line change
Expand Up @@ -40,12 +40,12 @@
.align 12
_mp_page_start:
/* Time base, MAS7 and machine check pin enable */
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
lis r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l
mtspr SPRN_HID0, r0

/* enable branch prediction */
lis r0, (BUCSR_ENABLE)@h
lis r0, (BUCSR_ENABLE)@h
ori r0, r0, (BUCSR_ENABLE)@l
mtspr SPRN_BUCSR, r0

Expand All @@ -55,15 +55,15 @@ _mp_page_start:
mttbu r3

/* Enable/invalidate the I-Cache */
lis r2, (L1CSR_CFI|L1CSR_CLFC)@h
lis r2, (L1CSR_CFI|L1CSR_CLFC)@h
ori r2, r2, (L1CSR_CFI|L1CSR_CLFC)@l
mtspr L1CSR1, r2
1:
mfspr r3, L1CSR1
and. r1, r3, r2
bne 1b

lis r3, (L1CSR_CPE|L1CSR_CE)@h
lis r3, (L1CSR_CPE|L1CSR_CE)@h
ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l
mtspr L1CSR1,r3
isync
Expand All @@ -81,7 +81,7 @@ _mp_page_start:
and. r1, r3, r2
bne 1b

lis r3, (L1CSR_CPE|L1CSR_CE)@h
lis r3, (L1CSR_CPE|L1CSR_CE)@h
ori r3, r3, (L1CSR_CPE|L1CSR_CE)@l
mtspr L1CSR0, r3
isync
Expand All @@ -91,7 +91,7 @@ _mp_page_start:
beq 2b

/* Get our PIR to figure out our table entry */
lis r3, TORESET(_spin_table)@h
lis r3, TORESET(_spin_table)@h
ori r3, r3, TORESET(_spin_table)@l

/* Determine base address for the core (use r10) */
Expand Down
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