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STM32H5: Tested sunny day boot
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- Temporarily decreased clock speed to 125MHz
- Test app working
- Re-mapped Nucleo board LEDs
- Tested on STM32H563ZI
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@danielinux
danielinux committed Mar 18, 2024
1 parent 7ae04c6 commit c85e306
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Showing 3 changed files with 83 additions and 59 deletions.
49 changes: 24 additions & 25 deletions hal/stm32h5.c
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,11 @@
static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
{
uint32_t reg = FLASH_ACR;
if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
if ((reg & FLASH_ACR_LATENCY_MASK) < waitstates)
do {
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
}
while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates);
}

void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
Expand All @@ -47,7 +50,7 @@ void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
void RAMFUNCTION hal_flash_clear_errors(uint8_t bank)
{
FLASH_SR |= ( FLASH_SR_WBNE | FLASH_SR_DBNE );

#if (TZ_SECURE())
FLASH_NS_SR |= ( FLASH_SR_WBNE | FLASH_SR_DBNE );
#endif
Expand Down Expand Up @@ -207,37 +210,35 @@ static void clock_pll_on(void)
{
uint32_t reg32;
uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
/* Select clock parameters (CPU Speed = 250 MHz) */

/* Select clock parameters (CPU Speed = 125 MHz) */
pllm = 4;
plln = 250;
plln = 125; /* TODO: increase to 250 MHz */
pllp = 2;
pllq = 2;
pllr = 2;
flash_waitstates = 5;

/* Set Vcore scale to 0 */
PWR_VOSCR &= ~PWR_VOS_MASK;
PWR_VOSCR |= PWR_VOS_SCALE_0;
while ((PWR_VOSSR & PWR_VOSRDY) == 0)
/* Disable PLL1 */
RCC_CR &= ~RCC_CR_PLL1ON;

/* Wait until PLL1 is disabled */
while ((RCC_CR & RCC_CR_PLL1RDY) != 0)
;

/* Set flash wait states */
flash_set_waitstates(flash_waitstates);

/* PLL Oscillator configuration */
RCC_CR |= RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT;

/* Wait until HSE is Ready */
while ((RCC_CR & RCC_CR_HSERDY) == 0)
;

/* Disable PLL1 */
RCC_CR &= ~RCC_CR_PLL1ON;

/* Wait until PLL1 is disabled */
while ((RCC_CR & RCC_CR_PLL1RDY) != 0)
;

/* Configure PLL1 div/mul factors */
reg32 = RCC_PLL1CFGR;
reg32 &= ~((0x3F << RCC_PLL1CFGR_PLL1M_SHIFT) | (0x03));
reg32 |= (pllm << RCC_PLL1CFGR_PLL1M_SHIFT) | RCC_PLL1CFGR_PLL1SRC_HSE;
RCC_PLL1CFGR = reg32;
DMB();
Expand Down Expand Up @@ -273,9 +274,6 @@ static void clock_pll_on(void)
/* Enable PLL1 */
RCC_CR |= RCC_CR_PLL1ON;

/* Set flash wait states */
flash_set_waitstates(flash_waitstates);

/* Set up APB3, 2, 1 and AHB prescalers */
hpre = RCC_AHB_PRESCALER_DIV_NONE;
apb1pre = RCC_APB_PRESCALER_DIV_NONE;
Expand All @@ -296,7 +294,8 @@ static void clock_pll_on(void)
;

/* Set PLL as clock source */
RCC_CFGR1 |= RCC_CFGR1_SW_PLL1;
reg32 = RCC_CFGR1 & (~RCC_CFGR1_SW_MASK);
RCC_CFGR1 = reg32 | RCC_CFGR1_SW_PLL1;
DMB();

/* Wait until selection of PLL as source is complete */
Expand Down Expand Up @@ -396,16 +395,16 @@ static void RAMFUNCTION fork_bootloader(void)
void hal_init(void)
{

#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
if ((FLASH_OPTSR_CUR & (FLASH_OPTSR_CUR_SWAP_BANK)) == 0)
fork_bootloader();
#endif

#if TZ_SECURE()
hal_tz_sau_init();
hal_gtzc_init();
#endif
clock_pll_on();
#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
if ((FLASH_OPTSR_CUR & (FLASH_OPTSR_CUR_SWAP_BANK)) == 0)
fork_bootloader();
#endif

}

Expand Down
9 changes: 5 additions & 4 deletions hal/stm32h5.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,10 @@
/*** RCC ***/
#if TZ_SECURE()
/*Secure */
#define RCC_BASE (0x50020c00) /* RM0481 - Table 3 */
#define RCC_BASE (0x54020c00) /* RM0481 - Table 3 */
#else
/*Non-Secure */
#define RCC_BASE (0x40020C00) /* RM0481 - Table 3 */
#define RCC_BASE (0x44020C00) /* RM0481 - Table 3 */
#endif

#define FLASH_SECURE_MMAP_BASE (0x0C000000)
Expand Down Expand Up @@ -78,6 +78,7 @@
#define RCC_CFGR1_SW_CSI (0x1)
#define RCC_CFGR1_SW_HSE (0x2)
#define RCC_CFGR1_SW_PLL1 (0x3)
#define RCC_CFGR1_SW_MASK (0x3)

/* HPRE - PPRE1 - PPRE2 - PPRE3 */
#define RCC_CFGR2_HPRE_SHIFT (0x0)
Expand Down Expand Up @@ -186,7 +187,7 @@
#define PWR_VOS_SCALE_0 (0x3 << 4) //RM0481 - 10.11.3
#define PWR_VOS_SCALE_3 (0x0 << 4) //RM0481 - 10.11.3 - Default on power up
#define PWR_VOS_MASK (0x3 << 4) //RM0481 - 10.11.3
#define PWR_VOSRDY (1 << 2) //RM0481 - 10.11.4 - Voltage scaling ready
#define PWR_VOSRDY (1 << 3) //RM0481 - 10.11.4 - Voltage scaling ready

#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
#define PWR_CR2_IOSV (1 << 9)
Expand Down Expand Up @@ -224,7 +225,7 @@
/* Non-Secure only */
#define FLASH_BASE (0x40022000) //RM0481 - Table 3
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x04))
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
#endif
Expand Down
84 changes: 54 additions & 30 deletions test-app/app_stm32h5.c
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Original file line number Diff line number Diff line change
Expand Up @@ -29,68 +29,92 @@
#include "hal.h"
#include "wolfboot/wolfboot.h"

#define LED_BOOT_PIN (7) /* PH7 - Discovery - Green Led */
#define LED_USR_PIN (6) /* PH6 - Discovery - Red Led */
#define LED_BOOT_PIN (4) /* PG4 - Nucleo - Red Led */
#define LED_USR_PIN (0) /* PB0 - Nucleo - Green Led */
#define LED_USR2_PIN (4) /* PF4 - Nucleo - Orange Led */

/*Non-Secure */
#define RCC_BASE (0x46020C00) /* RM0456 - Table 4 */
#define PWR_BASE (0x46020800) /* RM0456 - Table 4 */
#define GPIOH_BASE 0x42021C00
#define RCC_BASE (0x44020C00) /* RM0481 - Table 3 */
#define GPIOG_BASE 0x42021800
#define GPIOB_BASE 0x42020400
#define GPIOF_BASE 0x42021400


#define GPIOH_MODER (*(volatile uint32_t *)(GPIOH_BASE + 0x00))
#define GPIOH_PUPDR (*(volatile uint32_t *)(GPIOH_BASE + 0x0C))
#define GPIOH_BSRR (*(volatile uint32_t *)(GPIOH_BASE + 0x18))
#define GPIOG_MODER (*(volatile uint32_t *)(GPIOG_BASE + 0x00))
#define GPIOG_PUPDR (*(volatile uint32_t *)(GPIOG_BASE + 0x0C))
#define GPIOG_BSRR (*(volatile uint32_t *)(GPIOG_BASE + 0x18))

#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
#define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7)
#define GPIOB_MODER (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
#define GPIOB_PUPDR (*(volatile uint32_t *)(GPIOB_BASE + 0x0C))
#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))

#define GPIOF_MODER (*(volatile uint32_t *)(GPIOF_BASE + 0x00))
#define GPIOF_PUPDR (*(volatile uint32_t *)(GPIOF_BASE + 0x0C))
#define GPIOF_BSRR (*(volatile uint32_t *)(GPIOF_BASE + 0x18))

#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
#define PWR_CR2_IOSV (1 << 9)
#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
#define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
#define GPIOF_AHB2ENR1_CLOCK_ER (1 << 5)
#define GPIOB_AHB2ENR1_CLOCK_ER (1 << 1)

static void boot_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_BOOT_PIN;

RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
RCC_AHB2ENR1_CLOCK_ER|= GPIOG_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;

#if 0
/* Disabled, may not need it */
PWR_CR2 |= PWR_CR2_IOSV;
#endif

reg = GPIOH_MODER & ~(0x03 << (pin * 2));
GPIOH_MODER = reg | (1 << (pin * 2));
GPIOH_PUPDR &= ~(0x03 << (pin * 2));
GPIOH_BSRR |= (1 << (pin + 16));
reg = GPIOG_MODER & ~(0x03 << (pin * 2));
GPIOG_MODER = reg | (1 << (pin * 2));
GPIOG_PUPDR &= ~(0x03 << (pin * 2));
GPIOG_BSRR |= (1 << (pin));
}

static void boot_led_off(void)
{
GPIOH_BSRR |= (1 << (LED_BOOT_PIN));
GPIOG_BSRR |= (1 << (LED_BOOT_PIN + 16));
}

void usr_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_USR_PIN;

RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
RCC_AHB2ENR1_CLOCK_ER|= GPIOB_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;

reg = GPIOH_MODER & ~(0x03 << (pin * 2));
GPIOH_MODER = reg | (1 << (pin * 2));
GPIOH_PUPDR &= ~(0x03 << (pin * 2));
GPIOH_BSRR |= (1 << (pin + 16));
reg = GPIOB_MODER & ~(0x03 << (pin * 2));
GPIOB_MODER = reg | (1 << (pin * 2));
GPIOB_PUPDR &= ~(0x03 << (pin * 2));
GPIOB_BSRR |= (1 << (pin));
}

void usr_led_off(void)
{
GPIOH_BSRR |= (1 << (LED_USR_PIN));
GPIOB_BSRR |= (1 << (LED_USR_PIN + 16));
}

void usr2_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_USR2_PIN;

RCC_AHB2ENR1_CLOCK_ER|= GPIOF_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;

reg = GPIOF_MODER & ~(0x03 << (pin * 2));
GPIOF_MODER = reg | (1 << (pin * 2));
GPIOF_PUPDR &= ~(0x03 << (pin * 2));
GPIOF_BSRR |= (1 << (pin));
}

void usr2_led_off(void)
{
GPIOF_BSRR |= (1 << (LED_USR2_PIN + 16));
}

void main(void)
Expand All @@ -100,7 +124,7 @@ void main(void)
usr_led_on();
boot_led_off();
if (wolfBoot_current_firmware_version() > 1)
boot_led_on();
usr2_led_on();
while(1)
;
}

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