Support for Renesas RX72N with wolfBoot GCC RX and Make. Tested on RX…

…72N Envision Kit.

config/examples/renesas-rx72n.config

@@ -17,6 +17,9 @@ SPMATH?=1
 RAM_CODE?=0
 DUALBANK_SWAP?=0
 
+# reserve 1KB for wolfBoot header
+IMAGE_HEADER_SIZE=1024
+
 # Optionally switch to big endian data if MDE is set
 #BIG_ENDIAN=1
 
@@ -28,7 +31,7 @@ WOLFBOOT_ORIGIN=0xFFFF0000
 
 # wolfBoot partition size (64KB)
 BOOTLOADER_PARTITION_SIZE=0x10000
-# Application Partition Size (960KB)
+# Application Partition Size (1984KB)
 WOLFBOOT_PARTITION_SIZE?=0x1F0000
 
 # Location in Flash for Application Partition
@@ -41,3 +44,12 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFE0000
 
 # TSIP
 PKA?=0
+
+# Use optimization level 2 (default is -Os, which causes issues)
+#OPTIMIZATION_LEVEL=2
+
+# Include debug symbols (even for release build)
+#DEBUG_SYMBOLS=1
+
+# Location of reset entry point from start of flash
+#CFLAGS_EXTRA+=-DBOOT_ENTRY_OFFSET=0x2C

docs/Targets.md

@@ -2155,33 +2155,109 @@ c
 
 ## Renesas RX72N
 
-This example for `Renesas RX72N` demonstrates simple secure firmware update by wolfBoot. A sample application v1 is
-securely updated to v2. Both versions behave the same except displaying its version of v1 or v2.
-They are compiled by e2Studio and running on the target board.
+Tested on the RX72N ENVISION KIT (HMI development kit for IoT systems). This includes an onboard E2 Lite emulator.
 
-In this demo, you may download two versions of application binary file by Renesas Flash Programmer.
-You can download and execute wolfBoot by e2Studio debugger. Use a USB connection between PC and the
-board for the debugger and flash programmer.
+The Renesas RX72N is supported either natively with "make" or through e2Studio. If using e2Studio see [Readme.md](../IDE/Renesas/e2studio/RX72N/Readme.md).
 
-Flash Allocation:
+Default UART Serial on SCI2 at P12-RXD2 P13-TXD2. Use USB on CN8 to attach a Virtual USB COM port. This feaure is enabled with `DEBUG_UART=1`.
+
+Example Boot Output (with DEBUG_UART=1):
 
 ```
-+---------------------------+------------------------+-----+
-| B |H|                     |H|                      |     |
-| o |e|   Primary           |e|   Update             |Swap |
-| o |a|   Partition         |a|   Partition          |Sect |
-| t |d|                     |d|                      |     |
-+---------------------------+------------------------+-----+
-0xffc00000: wolfBoot
-0xffc10000: Primary partition (Header)
-0xffc10100: Primary partition (Application image) /* When it uses IMAGE_HEADER_SIZE 256, e.g. ED25519, EC256, EC384 or EC512 */
-0xffc10200: Primary partition (Application image) /* When it uses IMAGE_HEADER_SIZE 512, e.g. RSA2048, RSA3072 */
-0xffdf0000: Update  partition (Header)
-0xffdf0100: Update  partition (Application image)
-0xfffd0000: Swap sector
+wolfBoot HAL Init
+Boot partition: 0xFFC00000
+Image size 25932
+
+| ------------------------------------------------------------------- |
+| Renesas RX User Application in BOOT partition started by wolfBoot   |
+| ------------------------------------------------------------------- |
+
+wolfBoot HAL Init
+
+=== Boot Partition[ffe00000] ===
+Magic:    WOLF
+Version:  01
+Status:   ff (New)
+Tail Mgc: ˇˇˇˇ
+
+=== Update Partition[ffef0000] ===
+Magic:    ˇˇˇˇ
+Version:  00
+Status:   ff (New)
+Tail Mgc: ˇˇˇˇ
+
+Current Firmware Version: 1
+Hit any key to call wolfBoot_success the firmware.
 ```
 
-Detailed steps can be found at [Readme.md](../IDE/Renesas/e2studio/RX72N/Readme.md).
+Default Onboard Flash Memory Layout (4MB) (64KB sector):
+
+| Description       | Address    | Size                |
+| ----------------- | ---------- | ------------------- |
+| OFSM Option Mem   | 0xFE7F5D00 | 0x00000080 ( 128 B ) |
+| Application       | 0xFFC00000 | 0x001F0000 (1984 KB) |
+| Update            | 0xFFDF0000 | 0x001F0000 (1984 KB) |
+| Swap              | 0xFFFE0000 | 0x00010000 (  64 KB) |
+| wolfBoot          | 0xFFFF0000 | 0x00010000 (  64 KB) |
+
+To switch RX parts to big endian data use:
+
+```sh
+# Big Endian
+rfp-cli -if fine -t e2l -device RX72x -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -write32 0xFE7F5D00 0xFFFFFFF8
+OR
+# Little Endian
+rfp-cli -if fine -t e2l -device RX72x -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -write32 0xFE7F5D00 0xFFFFFFFF
+```
+
+## Building Renesas RX72N
+
+Building RX wolfBoot requires the RX-ELF compiler. Please Download and install the Renesas RX GCC toolchain:
+https://llvm-gcc-renesas.com/rx-download-toolchains/
+
+Default installation path (Linux): `~/toolchains/gcc_8.3.0.202311_rx_elf`
+Default installation path (Windows): `C:\ProgramData\GCC for Renesas RX 8.3.0.202305-GNURX-ELF\rx-elf\rx-elf`
+
+Configuration:
+Use `./config/examples/renesas-rx72n.config` as a starting point by copying it to the wolfBoot root as `.config`.
+
+```sh
+cp ./config/examples/renesas-rx72n.config .config
+make
+```
+
+With RX GCC path or or custom cross compiler directly:
+`make CROSS_COMPILE="~/toolchains/gcc_8.3.0.202311_rx_elf/bin/rx-elf-"`
+OR
+`make RX_GCC_PATH="~/toolchains/gcc_8.3.0.202311_rx_elf"`
+
+
+TSIP: To enable TSIP use `make PKA=1`
+
+## Flashing Renesas RX72N
+
+Download the Renesas Flashing Tool: https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui
+Download the Renesas E2 Lite Linux Driver: https://www.renesas.com/us/en/document/swo/e2-emulator-e2-emulator-lite-linux-driver?r=488806
+
+Default Flash ID Code: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+
+Flash Using:
+
+```
+rfp-cli -if fine -t e2l -device RX72x -auto -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF \
+    -bin FFFF0000 wolfboot.bin \
+    -bin FFC00000 test-app/image_v1_signed.bin \
+    -run
+```
+
+Note: Endianess: if using big endian add `-endian big`
+
+Note: Linux Install E2 Lite USB Driver:
+
+```sh
+sudo cp 99-renesas-emu.rules /etc/udev/rules.d/
+sudo udevadm control --reload-rules
+```
 
 
 ## Renesas RA6M4

hal/rx65n.c

@@ -32,7 +32,7 @@
 #include "hal.h"
 #include "hal/renesas-rx.h"
 
-#define SYS_CLK (240000000) /* 240MHz */
+#define SYS_CLK (120000000) /* 120MHz */
 #define PCLKA   (120000000) /* 120MHz */
 #define PCLKB   (60000000)  /* 60MHz */
 
@@ -107,19 +107,19 @@
 #define PROTECT_OFF() SYS_PRCR = (SYS_PRCR_PRKEY | SYS_PRCR_PRC0 | SYS_PRCR_PRC1 | SYS_PRCR_PRC3)
 #define PROTECT_ON()  SYS_PRCR = (SYS_PRCR_PRKEY)
 
-#define SYS_MOFCR   (*(volatile uint8_t *)(0x8C293))
+#define SYS_MOFCR   (*(volatile uint8_t *)(SYSTEM_BASE + 0xC293))
 #define SYS_MOFCR_MOFXIN      (1 << 0)  /* OSC Force Oscillation: 0=not controlled, 1=main clock forced */
 #define SYS_MOFCR_MODRV2(n) ((n) << 4)  /* OSC MHz: 0=20.1-24, 1=16.1-20, 2=8.1-16, 3=8 */
 #define SYS_MOFCR_MOSEL       (1 << 6)  /* 0=resonator, 1=external clk in*/
 
-#define SYS_HOCOPCR  (*(volatile uint8_t *)(0x8C294))
+#define SYS_HOCOPCR  (*(volatile uint8_t *)(SYSTEM_BASE + 0xC294))
 #define SYS_HOCOPCR_HOCOPCNT (1 << 0) /* High-Speed On-Chip Oscillator Power Supply Control: 0=On, 1=Off */
 
-#define SYS_RSTSR1  (*(volatile uint8_t *)(0x8C291))
+#define SYS_RSTSR1  (*(volatile uint8_t *)(SYSTEM_BASE + 0xC291))
 #define SYS_RSTSR1_CWSF (1 << 0) /* 0=Cold Start, 1=Warm Start */
 
 /* RTC */
-#define RTC_BASE 0x8C400
+#define RTC_BASE (SYSTEM_BASE + 0xC400)
 #define RTC_RCR3 (*(volatile uint8_t *)(RTC_BASE + 0x26))
 #define RTC_RCR3_RTCEN      (1 << 0) /* Sub Clock Osc: 0=stopped, 1=operating */
 #define RTC_RCR3_RTCDV(n) ((n) << 1)
@@ -132,7 +132,7 @@
 #define FLASH_ROMWT_ROMWT(n) ((n) << 0) /* 0=no wait, 1=one wait cycle, 2=two wait cycles */
 
 /* Serial Communication Interface */
-#define SCI_BASE(n) (0x8A000 + ((n) * 0x20))
+#define SCI_BASE(n) (SYSTEM_BASE + 0xA000 + ((n) * 0x20))
 #define SCI_SMR(n)  (*(volatile uint8_t *)(SCI_BASE(n) + 0x00))
 #define SCI_SMR_CKS(clk) (clk & 0x3) /* 0=PCLK, 1=PCLK/4, 2=PCLK/16, 3=PCLK/64 */
 #define SCI_SMR_STOP  (1 << 3) /* 0=1 stop bit */
@@ -169,14 +169,14 @@
 #define SCI_SPMR_CKPH  (1 << 7) /* Clock Phase: 0=not delayed, 1=delayed */
 
 /* MPC (Multi-Function Pin Controller) */
-#define MPC_PWPR   (*(volatile uint8_t *)(0x8C11F))
+#define MPC_PWPR   (*(volatile uint8_t *)(SYSTEM_BASE + 0xC11F))
 #define MPC_PWPR_B0WI  (1 << 7)
 #define MPC_PWPR_PFSWE (1 << 6)
 
-#define MPC_PFS(n) (*(volatile uint8_t *)(0x8C0E0 + (n)))
+#define MPC_PFS(n) (*(volatile uint8_t *)(SYSTEM_BASE + 0xC0E0 + (n)))
 
 /* Ports */
-#define PORT_BASE    (0x8C000)
+#define PORT_BASE    (SYSTEM_BASE + 0xC000)
 #define PORT_PDR(n)  (*(volatile uint8_t*)(PORT_BASE + 0x00 + (n))) /* Port Direction Register: 0=Input, 1=Output */
 #define PORT_PODR(n) (*(volatile uint8_t*)(PORT_BASE + 0x20 + (n))) /* Port Output Data Register: 0=Low, 1=High */
 #define PORT_PIDR(n) (*(volatile uint8_t*)(PORT_BASE + 0x40 + (n))) /* Port Input Register: 0=Low input, 1=Hight Input */
@@ -186,7 +186,7 @@
 #define PORT_DSCR(n) (*(volatile uint8_t*)(PORT_BASE + 0xE0 + (n))) /* Drive Capacity Control Register: 0=Normal, 1=High-drive output */
 
 /* RSPI */
-#define RSPI_BASE(n)     (0xD0100 + ((n) * 0x40)) /* n=0-2 (RSPI0,RSPI1,RSPI2) */
+#define RSPI_BASE(n)     (SYSTEM_BASE + 0x50100 + ((n) * 0x40)) /* n=0-2 (RSPI0,RSPI1,RSPI2) */
 #define RSPI_SPCR(n)     (*(volatile uint8_t *)(RSPI_BASE(n) + 0x00)) /* Control */
 #define RSPI_SPCR_SPMS      (1 << 0) /* RSPI Mode Select 0=SPI operation (4-wire method) */
 #define RSPI_SPCR_TXMD      (1 << 1)
@@ -529,7 +529,7 @@ void hal_clk_init(void)
     #define PLL_MUL_STC (((uint8_t)((float)CFG_PLL_MUL * 2.0)) - 1)
     reg = (
         SYS_PLLCR_PLIDIV(CFD_PLL_DIV) | /* no div */
-        PLL_SRCSEL |                    /* clock source (0=main, 1=HOCO */
+        PLL_SRCSEL |                    /* clock source (0=main, 1=HOCO) */
         SYS_PLLCR_STC(PLL_MUL_STC)      /* multiplier */
     );
     SYS_PLLCR = reg;