Fixes for DDR errata and enabling timebase for udelay().

hal/nxp_p1021.c

@@ -419,7 +419,6 @@ enum elbc_amask_sizes {
 #define DDR_SDRAM_MODE     ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */
 #define DDR_SDRAM_MODE_2   ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */
 #define DDR_SDRAM_MD_CNTL  ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
-#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
 #define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
 
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */

hal/nxp_ppc.h

@@ -216,6 +216,7 @@
 
     /* CoreNet on-chip interface between the core cluster and rest of SoC */
     #define USE_CORENET_INTERFACE
+    #define HAS_EMBEDDED_HYPERVISOR /* E.HV Supported */
 
     /* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */
     #define BOOKE_PAGESZ_4K    2
@@ -317,6 +318,7 @@
 #define MAS3     0x273
 #define MAS6     0x276
 #define MAS7     0x3B0
+#define MAS8     0x155
 #define MMUCSR0  0x3F4 /* MMU control and status register 0 */
 
 #define MAS0_TLBSEL_MSK 0x30000000

hal/nxp_t1024.c

@@ -80,10 +80,16 @@ static int test_tpm(void);
 #define GUTS_BASE      (CCSRBAR + 0xE0000)
 #define GUTS_PVR       ((volatile uint32_t*)(GUTS_BASE + 0xA0UL))
 #define GUTS_SVR       ((volatile uint32_t*)(GUTS_BASE + 0xA4UL))
-#define GUTS_DEVDISR   ((volatile uint32_t*)(GUTS_BASE + 0x70UL)) /* Device disable register */
+#define GUTS_DEVDISR1  ((volatile uint32_t*)(GUTS_BASE + 0x70UL)) /* Device disable register */
+#define GUTS_DEVDISR2  ((volatile uint32_t*)(GUTS_BASE + 0x74UL)) /* Device disable register */
+#define GUTS_DEVDISR3  ((volatile uint32_t*)(GUTS_BASE + 0x78UL)) /* Device disable register */
+#define GUTS_DEVDISR4  ((volatile uint32_t*)(GUTS_BASE + 0x7CUL)) /* Device disable register */
+#define GUTS_DEVDISR5  ((volatile uint32_t*)(GUTS_BASE + 0x80UL)) /* Device disable register */
+#define GUTS_COREDISR  ((volatile uint32_t*)(GUTS_BASE + 0x94UL)) /* Core Enable/Disable */
 
-#define GUTS_DEVDISR_TB0    0x00004000
-#define GUTS_DEVDISR_TB1    0x00001000
+#define RCPM_PCTBENR    ((volatile uint32_t*)(CCSRBAR + 0xE21A0)) /* Physical Core Time Base Enable Bit 0=Core 0 */
+#define RCPM_PCTBCKSELR ((volatile uint32_t*)(CCSRBAR + 0xE21A4)) /* Physical Core Time Base Clock Select 0=Platform Clock/16, 1=RTC */
+#define RCPM_TBCLKDIVR  ((volatile uint32_t*)(CCSRBAR + 0xE21A8)) /* Time Base Clock Divider 0=1/16, 1=1/8, 2=1/24, 3=1/32 */
 
 /* MPIC - T1024RM 24.3 */
 #define PIC_BASE    (CCSRBAR + 0x40000)
@@ -377,15 +383,18 @@ enum ifc_amask_sizes {
 #define DDR_SDRAM_MODE_7   ((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
 #define DDR_SDRAM_MODE_8   ((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
 #define DDR_SDRAM_MD_CNTL  ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
-#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
 #define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
 
+#define DDR_DEBUG_19       ((volatile uint32_t*)(DDR_BASE + 0xF48))
+#define DDR_DEBUG_29       ((volatile uint32_t*)(DDR_BASE + 0xF70))
+
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */
 #define DDR_SDRAM_CFG_32_BE    0x00080000
 #define DDR_SDRAM_CFG_ECC_EN   0x20000000
 #define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
 #define DDR_SDRAM_CFG_BI       0x00000001 /* Bypass initialization */
 
+#define DDR_SDRAM_INTERVAL_BSTOPRE 0x3FFF
 
 
 /* eSPI */
@@ -438,7 +447,7 @@ static uint32_t hal_get_bus_clk(void)
 
 static void udelay(unsigned long delay_us)
 {
-    delay_us *= (hal_get_bus_clk() / 1000000);
+    delay_us *= (SYS_CLK / 16) / 1000000;
     wait_ticks(delay_us);
 }
 
@@ -652,6 +661,9 @@ void hal_ddr_init(void)
 #ifdef ENABLE_DDR
     uint32_t reg;
 
+    /* enable timebase on core 0 */
+    set32(RCPM_PCTBENR, (1 << 0));
+
     /* If DDR is already enabled then just return */
     if (get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) {
         return;
@@ -695,7 +707,8 @@ void hal_ddr_init(void)
     set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL);
 
     /* DDR Configuration */
-    set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL);
+    /* Errata A-009663 - DRAM VRef training (do not set precharge interval till after enable) */
+    set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL & ~DDR_SDRAM_INTERVAL_BSTOPRE);
     set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL);
     set32(DDR_DATA_INIT, DDR_DATA_INIT_VAL);
     set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL);
@@ -718,13 +731,44 @@ void hal_ddr_init(void)
     set32(DDR_SDRAM_CFG, (DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN));
     asm volatile("sync;isync");
 
+    /* busy wait for ~500us */
+    udelay(500);
+    asm volatile("sync;isync");
+
     /* Enable controller */
     reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
     set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN);
     asm volatile("sync;isync");
 
-    /* Wait for data initialization is complete */
-    while ((get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT));
+    /* Errata A-008378: training in DDR4 mode */
+    /* write to DEBUG_29[8:11] a value of 4'b1001 before controller is enabled */
+    reg = get32(DDR_DEBUG_29);
+    reg |= (0x9 << 20);
+    set32(DDR_DEBUG_29, reg);
+
+    /* Errata A-008109: Memory controller could fail to complete initialization */
+    reg = get32(DDR_SDRAM_CFG_2);
+    reg |= 0x800; /* set DDR_SLOW */
+    set32(DDR_SDRAM_CFG_2, reg);
+    reg = get32(DDR_DEBUG_19);
+    reg |= 0x2;
+    set32(DDR_DEBUG_19, reg);
+    set32(DDR_DEBUG_29, 0x30000000);
+
+    /* Errata A-009942: DDR controller can train to non-optimal setting */
+    reg = get32(DDR_DEBUG_29);
+    reg &= ~0xFF0FFF00;
+    reg |= 0x0070006F; /* DDR-1400/1500/1600 */
+    set32(DDR_DEBUG_29, reg);
+
+    /* Wait for data initialization to complete */
+    while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) {
+        /* busy wait loop - throttle polling */
+        udelay(1);
+    }
+
+    /* Errata A-009663 - Write real precharge interval */
+    set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL);
 
     /* DDR - TBL=1, Entry 12/13 */
     set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS,

hal/nxp_t2080.c

@@ -288,7 +288,6 @@ enum ifc_amask_sizes {
 #define DDR_SDRAM_MODE_7   *((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */
 #define DDR_SDRAM_MODE_8   *((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */
 #define DDR_SDRAM_MD_CNTL  *((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
-#define DDR_SDRAM_INTERVAL *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
 #define DDR_SDRAM_CLK_CNTL *((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
 
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */

options.mk

@@ -616,6 +616,10 @@ endif
 ifeq ($(ELF),1)
   CFLAGS+=-DWOLFBOOT_ELF
   OBJS += src/elf.o
+
+  ifneq ($(DEBUG_ELF),)
+    CFLAGS+=-DDEBUG_ELF=$(DEBUG_ELF)
+  endif
 endif
 
 ifeq ($(MULTIBOOT2),1)

src/boot_ppc_start.S

@@ -144,20 +144,22 @@ reset_exceptions:
         mttbl   r0 /* prevent FIT and WDT exceptions */
         mttbu   r0
         mtspr   SPRN_TSR, r1 /* clear all timer exception status */
-#ifdef PLATFORM_nxp_p1021
         mtspr   SPRN_TCR, r0 /* disable all timers */
-#endif
         mtspr   SPRN_ESR, r0 /* clear exception syndrome register */
         mtspr   SPRN_MCSR, r0 /* clear machine check syndrome register */
         mtxer   r0 /* clear integer exception register */
 
+#if defined(CORE_E5500) || defined(CORE_E6500)
+        mtspr MAS8, r0 /* clear MAS8 used with Embedded Hypervisor */
+#endif
+
 hardware_reg:
         /* Time base, MAS7 and machine check pin enable */
         lis     r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@h
         ori     r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l
         mtspr   SPRN_HID0, r0
 
-#if defined(PLATFORM_nxp_p1021) && !defined(BUILD_LOADER_STAGE1)
+#if defined(CORE_E500) && !defined(BUILD_LOADER_STAGE1)
         /* Set addr streaming & broadcast
          * and optimized sync instruction (if rev 5.0 or greater) */
         li      r0, (HID1_ASTME | HID1_ABE)@l
@@ -417,8 +419,7 @@ ccsr_tlb:
                 MAS3_SX | MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0,
                 CCSRBAR_SIZE, 1, r3);
 
-#if defined(CORE_E6500)
-        /* Note: Setting CCSR LAW for CORE_E5500 is not required */
+#if defined(CORE_E5500) || defined(CORE_E6500)
 ccsr_law:
         /* CCSR - LAW0 (CoreNet 16MB) */
         #define CCSR_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_16MB)
@@ -436,7 +437,7 @@ ccsr_law:
         stw     r2, 8(r9) /* LAWAR */
         lwz     r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
         isync
-#endif /* CORE_E6500 */
+#endif /* CORE_E5500 || CORE_E6500 */
 
 #ifdef FLASH_BASE_ADDR
 #if defined(CORE_E5500) || defined(CORE_E6500)
@@ -763,7 +764,7 @@ cache_sram_init_loop:
         /* Data cache block zero */
         dcbz    r0, r3
         /* Data cache block touch and lock set */
-#if defined(CORE_E5500) || defined(CORE_E6500)
+#if defined(CORE_E6500)
         dcbtls  2, r0, r3
         dcbtls  0, r0, r3
 #else

src/elf.c

@@ -34,9 +34,10 @@
 
 /* support for elf parsing debug printf */
 #if defined(DEBUG) || defined(ELF_PARSER)
-#if DEBUG_ELF == 0
+#if defined(DEBUG_ELF) && DEBUG_ELF == 0
 #undef DEBUG_ELF
 #else
+#undef  DEBUG_ELF
 #define DEBUG_ELF
 #endif
 #endif