Fixes for NXP T1024 and booting Integrity OS:

* Fixed PPC spin table based on ePAPR 1.1.
* Added flattened device tree (FDT) support. Setting required FDT fields per ePAPR 1.1.
* Added Frame Manager microcode upload.
* Fixed CPLD and setting QE clock.
* Added support for setting logical device numbers and updated device tree.
* Fixed QUICC Engine base address (was incorrect, should be 0x140000).
* Fixed "cpu-release-addr" to use 64-bit value.
* Added secondary cached boot page.
* Added L2 cache support to multi-core.
* Added flattened device tree parser tool for testing (`make fdt-parser` and `tools/fdt-parser/fdt-parser`).
* Added checks for FDT header.
* Added automated test case for NXP T1024 FDT.

.github/workflows/test-parse-tools.yml

@@ -0,0 +1,46 @@
+name: Test parsing tools (elf and fdt)
+
+on:
+  push:
+    branches: [ 'master', 'main', 'release/**' ]
+  pull_request:
+    branches: [ '*' ]
+
+jobs:
+
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: true
+
+      - name: Install cross compilers
+        run: |
+          sudo apt-get install -y gcc-arm-none-eabi gcc-powerpc-linux-gnu
+
+      - name: make distclean
+        run: |
+          make distclean
+
+      - name: Select config
+        run: |
+          cp config/examples/nxp-t1024.config .config
+
+      - name: Build wolfBoot
+        run: |
+          make
+
+      - name: Build tools
+        run: |
+          make elf-parser
+          make fdt-parser
+
+      - name: Run elf-parser test
+        run: |
+          ./tools/elf-parser/elf-parser
+
+      - name: Run fdt-parser test (nxp_t1024.dtb)
+        run: |
+          ./tools/fdt-parser/fdt-parser ./tools/fdt-parser/nxp_t1024.dtb -t

.gitignore

@@ -100,6 +100,7 @@ tools/uart-flash-server/ufserver
 tools/unit-tests/unit-parser
 tools/bin-assemble/bin-assemble
 tools/elf-parser/elf-parser
+tools/fdt-parser/fdt-parser
 tools/tpm/rot
 tools/tpm/pcr_read
 tools/tpm/pcr_reset

Makefile

@@ -276,6 +276,7 @@ utilsclean: clean
 	$(Q)$(MAKE) -C tools/delta -s clean
 	$(Q)$(MAKE) -C tools/bin-assemble -s clean
 	$(Q)$(MAKE) -C tools/elf-parser -s clean
+	$(Q)$(MAKE) -C tools/fdt-parser -s clean
 	$(Q)$(MAKE) -C tools/check_config -s clean
 	$(Q)$(MAKE) -C tools/test-expect-version -s clean
 	$(Q)$(MAKE) -C tools/test-update-server -s clean
@@ -313,6 +314,10 @@ elf-parser:
 	@$(MAKE) -C tools/elf-parser -s clean
 	@$(MAKE) -C tools/elf-parser
 
+fdt-parser:
+	@$(MAKE) -C tools/fdt-parser -s clean
+	@$(MAKE) -C tools/fdt-parser
+
 config: FORCE
 	$(MAKE) -C config
 

arch.mk

@@ -424,6 +424,7 @@ ifeq ($(TARGET),nxp_t1024)
   LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
   LDFLAGS+=-Wl,--as-needed # remove weak functions not used
   OBJS+=src/boot_ppc_mp.o # support for spin table
+  OBJS+=src/fdt.o
   UPDATE_OBJS:=src/update_ram.o
   ifeq ($(SPMATH),1)
     MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
@@ -445,6 +446,7 @@ ifeq ($(TARGET),nxp_t2080)
   LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
   LDFLAGS+=-Wl,--as-needed # remove weak functions not used
   UPDATE_OBJS:=src/update_ram.o
+  OBJS+=src/fdt.o
   ifeq ($(SPMATH),1)
     MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
   else
@@ -750,6 +752,7 @@ BOOT_IMG?=test-app/image.bin
 ## Update mechanism
 ifeq ($(ARCH),AARCH64)
   CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+  OBJS+=src/fdt.o
   UPDATE_OBJS:=src/update_ram.o
 endif
 ifeq ($(DUALBANK_SWAP),1)

hal/nxp_p1021.c

@@ -22,22 +22,24 @@
 #include "target.h"
 #include "image.h"
 #include "printf.h"
-#include <string.h>
+#include "string.h"
 
 #include "nxp_ppc.h"
 
 /* Debugging */
 /* #define DEBUG_EXT_FLASH */
 /* #define DEBUG_ESPI 1 */
 
-/* Tests */
-/* #define TEST_DDR */
-/* #define TEST_FLASH */
-/* #define TEST_TPM */
-
 #define ENABLE_ELBC /* Flash Controller */
 #define ENABLE_BUS_CLK_CALC
+
 #ifndef BUILD_LOADER_STAGE1
+    /* Tests */
+    #if 0
+        #define TEST_DDR
+        #define TEST_FLASH
+        #define TEST_TPM
+    #endif
     #define ENABLE_PCIE
     #define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */
     #define ENABLE_CONF_IO
@@ -50,6 +52,7 @@
     /* #define ENABLE_QE_CRC32 */ /* CRC32 check on QE disabled by default */
 #endif
 
+/* Foward declarations */
 #if defined(ENABLE_DDR) && defined(TEST_DDR)
 static int test_ddr(void);
 #endif
@@ -421,8 +424,8 @@ enum elbc_amask_sizes {
 #define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
 
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */
-#define DDR_SDRAM_CFG_32_BE    0x00080000
 #define DDR_SDRAM_CFG_ECC_EN   0x20000000
+#define DDR_SDRAM_CFG_32_BE    0x00080000
 #define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
 #define DDR_SDRAM_CFG_BI       0x00000001 /* Bypass initialization */
 
@@ -894,7 +897,7 @@ static void hal_ddr_init(void)
     /* Map LAW for DDR */
     set_law(6, 0, DDR_ADDRESS, LAW_TRGT_DDR, LAW_SIZE_512MB, 0);
 
-    /* If DDR is not already enabled */
+    /* If DDR is already enabled then just return */
     if ((get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN)) {
         return;
     }
@@ -1379,7 +1382,7 @@ static int hal_qe_init(void)
         set32(QE_SDMA_SDAQMR, 0);
 
         /* Allocate 2KB temporary buffer for sdma */
-        sdma_base = 0;
+        sdma_base = 0; /* offset in QE_MURAM */
         set32(QE_SDMA_SDEBCR, sdma_base & QE_SDEBCR_BA_MASK);
 
         /* Clear sdma status */
@@ -1401,28 +1404,25 @@ static int hal_qe_init(void)
 #ifdef ENABLE_MP
 
 /* from boot_ppc_core.S */
-extern uint32_t _mp_page_start;
+extern uint32_t _secondary_start_page;
+extern uint32_t _second_half_boot_page;
 extern uint32_t _spin_table;
+extern uint32_t _spin_table_addr;
 extern uint32_t _bootpg_addr;
 
 /* Startup additional cores with spin table and synchronize the timebase */
 static void hal_mp_up(uint32_t bootpg)
 {
     uint32_t up, cpu_up_mask, whoami, bpcr, devdisr;
-    uint8_t *spin_table_addr;
     int timeout = 50, i;
 
     /* Get current running core number */
     whoami = get32(PIC_WHOAMI);
 
-    /* Calculate location of spin table in BPTR */
-    spin_table_addr = (uint8_t*)(BOOT_ROM_ADDR +
-        ((uint32_t)&_spin_table - (uint32_t)&_mp_page_start));
-
-    wolfBoot_printf("MP: Starting core 2 (spin table %p)\n",
-        spin_table_addr);
+    wolfBoot_printf("MP: Starting core 2 (boot page %p, spin table %p)\n",
+        bootpg, (uint32_t)&_spin_table);
 
-    /* Set the boot page translation reigster */
+    /* Set the boot page translation register */
     set32(RESET_BPTR, RESET_BPTR_EN | RESET_BPTR_BOOTPG(bootpg));
 
     /* Disable time base on inactive core */
@@ -1444,8 +1444,8 @@ static void hal_mp_up(uint32_t bootpg)
     cpu_up_mask = (1 << whoami);
     while (timeout) {
         for (i = 0; i < CPU_NUMCORES; i++) {
-            uint32_t* entry = (uint32_t*)(spin_table_addr +
-                (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
+            uint32_t* entry = (uint32_t*)(
+                  (uint8_t*)&_spin_table + (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
             if (*entry) {
                 cpu_up_mask |= (1 << i);
             }
@@ -1480,23 +1480,29 @@ static void hal_mp_up(uint32_t bootpg)
 
 static void hal_mp_init(void)
 {
-    uint32_t *fixup = (uint32_t*)&_mp_page_start;
+    uint32_t *fixup = (uint32_t*)&_secondary_start_page;
     uint32_t bootpg;
     int i_tlb = 0; /* always 0 */
     size_t i;
-    const uint32_t *s;
-    uint32_t *d;
+    const volatile uint32_t *s;
+    volatile uint32_t *d;
 
     /* Assign virtual boot page at end of DDR */
     bootpg = DDR_ADDRESS + DDR_SIZE - BOOT_ROM_SIZE;
 
     /* Store the boot page address for use by additional CPU cores */
-    _bootpg_addr = bootpg;
+    _bootpg_addr = (uint32_t)&_second_half_boot_page;
+
+    /* Store location of spin table for other cores */
+    _spin_table_addr = (uint32_t)&_spin_table;
+
+    /* Flush bootpg before copying to invalidate any stale cache lines */
+    flush_cache(bootpg, BOOT_ROM_SIZE);
 
-    /* map reset page to bootpg so we can copy code there */
+    /* Map reset page to bootpg so we can copy code there */
     disable_tlb1(i_tlb);
-    set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */
-        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
+    set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn, urpn */
+        (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), /* perms, wimge */
         0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
     /* copy startup code to virtually mapped boot address */

hal/nxp_p1021.ld

@@ -39,6 +39,8 @@ SECTIONS
     {
         _start_vector = .;
         KEEP(*(.isr_vector))
+        . = ALIGN(256);
+        KEEP(*(.bootmp))
         *(.text*)
         *(.rodata*)
         *(.sdata*)

hal/nxp_ppc.h

@@ -32,7 +32,9 @@
     #define CCSRBAR_SIZE BOOKE_PAGESZ_1M
 
     #define ENABLE_DDR
+    #ifndef DDR_SIZE
     #define DDR_SIZE (512UL * 1024UL * 1024UL)
+    #endif
 
     /* Memory used for transferring blocks to/from NAND.
      * Maps to eLBC FCM internal 8KB region (by hardware) */
@@ -62,8 +64,9 @@
 
 #elif defined(PLATFORM_nxp_t1024)
     /* NXP T1024 */
-    #define CPU_NUMCORES 2
     #define CORE_E5500
+    #define CPU_NUMCORES 2
+    #define CORES_PER_CLUSTER 1
     #define LAW_MAX_ENTRIES 16
 
     #define CCSRBAR_DEF (0xFE000000) /* T1024RM 4.4.1 default base */
@@ -86,7 +89,9 @@
     #endif
 
     #define ENABLE_DDR
+    #ifndef DDR_SIZE
     #define DDR_SIZE (2048ULL * 1024ULL * 1024ULL)
+    #endif
 
     #define FLASH_BASE_ADDR      0xEC000000UL
     #define FLASH_BASE_PHYS_HIGH 0xFULL
@@ -97,9 +102,11 @@
 
 #elif defined(PLATFORM_nxp_t2080)
     /* NXP T0280 */
-    #define CPU_NUMCORES 4
     #define CORE_E6500
+    #define CPU_NUMCORES 4
+    #define CORES_PER_CLUSTER 4
     #define LAW_MAX_ENTRIES 32
+    #define ENABLE_PPC64
 
     #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
@@ -122,7 +129,9 @@
     #define ENABLE_INTERRUPTS
 
     #define ENABLE_DDR
+    #ifndef DDR_SIZE
     #define DDR_SIZE (8192UL * 1024UL * 1024UL)
+    #endif
 
     #define FLASH_BASE_ADDR      0xE8000000UL
     #define FLASH_BASE_PHYS_HIGH 0x0ULL
@@ -424,11 +433,32 @@
 
 /* L2 Cache */
 #if defined(CORE_E6500)
+    /* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
+    #define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
+    #define L2PID(n)           (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
+    #define L2PIR(n)           (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
+    #define L2PWR(n)           (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */
+
     /* MMRs */
     #define L2CSR0    0x000 /* L2 Cache Control and Status 0 */
     #define L2CSR1    0x004 /* L2 Cache Control and Status 1 */
     #define L2CFG0    0x008 /* L2 Cache Configuration */
 #else
+    #ifdef CORE_E5500
+        /* L2 Cache Control - E5500RM 2.15 L2 Cache Registers */
+        #define L2_BASE         (CCSRBAR + 0x20000)
+    #else
+        /* E500 */
+        #define L2_BASE         (CCSRBAR + 0x20000)
+        #define L2CTL           0x000 /* 0xFFE20000 - L2 control register */
+        #define L2SRBAR0        0x100 /* 0xFFE20100 - L2 SRAM base address register */
+
+        #define L2CTL_EN        (1 << 31) /* L2 enable */
+        #define L2CTL_INV       (1 << 30) /* L2 invalidate */
+        #define L2CTL_SIZ(n)    (((n) & 0x3) << 28) /* 2=256KB (always) */
+        #define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
+    #endif
+
     /* SPR */
     #define L2CFG0    0x207 /* L2 Cache Configuration Register 0 */
     #define L2CSR0    0x3F9 /* L2 Data Cache Control and Status Register 0 */
@@ -441,8 +471,6 @@
 #define L2CSR0_L2PE  0x40000000 /* L2 Cache Parity/ECC Enable */
 #define L2CSR0_L2E   0x80000000 /* L2 Cache Enable */
 
-#define L2CSR0_L2E   0x80000000 /* L2 Cache Enable */
-#define L2CSR0_L2PE  0x40000000 /* L2 Cache Parity/ECC Enable */
 #define L2CSR0_L2WP  0x1c000000 /* L2 I/D Way Partioning */
 #define L2CSR0_L2CM  0x03000000 /* L2 Cache Coherency Mode */
 #define L2CSR0_L2FI  0x00200000 /* L2 Cache Flash Invalidate */
@@ -702,17 +730,24 @@ extern void dcache_disable(void);
     #define r31 31
 #endif
 
+/* ePAPR 1.1 spin table */
 /* For multiple core spin table communication */
-#define EPAPR_MAGIC       (0x45504150)
+/* The spin table must be WING 0b001x (memory-coherence required) */
+/* For older PPC compat use dcbf to flush spin table entry */
+/* Note: spin-table must be cache-line aligned in memory */
+#define EPAPR_MAGIC       (0x45504150) /* Book III-E CPUs */
 #define ENTRY_ADDR_UPPER  0
 #define ENTRY_ADDR_LOWER  4
 #define ENTRY_R3_UPPER    8
 #define ENTRY_R3_LOWER    12
 #define ENTRY_RESV        16
 #define ENTRY_PIR         20
+
+/* not used for ePAPR 1.1 */
 #define ENTRY_R6_UPPER    24
 #define ENTRY_R6_LOWER    28
-#define ENTRY_SIZE        32
 
 
+#define ENTRY_SIZE        64
+
 #endif /* !_NXP_PPC_H_ */